Uros Bizjak <ubiz...@gmail.com> 于2023年12月5日周二 18:46写道：
> > On Tue, Dec 5, 2023 at 3:29 AM Hongyu Wang <hongyu.w...@intel.com> wrote: > > > > Under APX NDD, previous TImode allocation will have issue that it was > > originally allocated using continuous pair, like rax:rdi, rdi:rdx. > > > > This will cause issue for all TImode NDD patterns. For NDD we will not > > assume the arithmetic operations like add have dependency between dest > > and src1, then write to 1st highpart rdi will be overrided by the 2nd > > lowpart rdi if 2nd lowpart rdi have different src as input, then the write > > to 1st highpart rdi will missed and cause miscompliation. > > > > To resolve this, under TARGET_APX_NDD we'd only allow register with even > > regno to be allocated with TImode, then TImode registers will be allocated > > with non-overlapping pairs. > > Perhaps you could use earlyclobber with __doubleword instructions: > > (define_insn_and_split "*add<dwi>3_doubleword" > [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r") > (plus:<DWI> > (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0") > (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o"))) > (clobber (reg:CC FLAGS_REG))] > > For the above pattern, you can add earlyclobbered &r output > alternative that guarantees that output won't be allocated to any of > the input registers. > Yes, it does resolve the dest/src overlapping issue we met, thanks! I tried it and no fails in gcc-testsuite and spec. Suppose for different src1/src2 RA can handle them correctly. Will update in V3 patches with the changes of get_attr_isa (insn) == ISA_APX_NDD
