From: Kong Lingling <lingling.k...@intel.com>
Legacy adc patterns are commonly adopted to TImode add, when extending TImode
add to NDD version, operands[0] and operands[1] can be different, so extra move
should be emitted if those patterns have optimization when adding const0_rtx.
For TImode insn, there could be register overlapping between operands[0]
and operands[1] as x86 allocates TImode register sequentially like rax:rdi,
rdi:rdx. After postreload split for TImode, write to 1st highpart rdi will
be overrided by the 2nd lowpart rdi if 2nd lowpart rdi have different src as
input, then the write to 1st highpart rdi will missed and cause miscompliation.
In addition, when input operands contain memory, the address register may also
overlaps with dest register if it is marked dead after one of highpart/lowpart
operation was done.
So the earlyclobber modifier '&' should be added to NDD dest to avoid
overlapping between dest and src operands.
NDD instructions will automatically zero-extend dest register to 64bit, so for
zext patterns it can adopt all NDD form that have memory src input.
gcc/ChangeLog:
* config/i386/i386.md (*add<dwi>3_doubleword): Add ndd alternatives,
adopt '&' to ndd dest and move operands[1] to operands[0] when they are
not equal.
(*add<dwi>3_doubleword_cc_overflow_1): Likewise.
(*addv<dwi>4_doubleword): Likewise.
(*addv<dwi>4_doubleword_1): Likewise.
(*add<dwi>3_doubleword_zext): Likewise.
(addv<mode>4_overflow_1): Add ndd alternatives.
(*addv<mode>4_overflow_2): Likewise.
(@add<mode>3_carry): Likewise.
(*add<mode>3_carry_0): Likewise.
(*addsi3_carry_zext): Likewise.
(addcarry<mode>): Likewise.
(addcarry<mode>_0): Likewise.
(*addcarry<mode>_1): Likewise.
(*add<mode>3_eq): Likewise.
(*add<mode>3_ne): Likewise.
(*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for
operands[1] to accept memory input for NDD alternative.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd-adc.c: New test.
---
gcc/config/i386/i386.md | 193 ++++++++++++--------
gcc/testsuite/gcc.target/i386/apx-ndd-adc.c | 15 ++
2 files changed, 136 insertions(+), 72 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a1626121227..8dd8216041e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6294,12 +6294,12 @@ (define_expand "add<mode>3"
TARGET_APX_NDD); DONE;")
(define_insn_and_split "*add<dwi>3_doubleword"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
(plus:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o")))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand"
"r<di>,o,r<di>,r")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
@@ -6319,24 +6319,34 @@ (define_insn_and_split "*add<dwi>3_doubleword"
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
if (operands[2] == const0_rtx)
{
+ /* Under NDD op0 and op1 may not equal, do not delete insn then. */
+ bool emit_insn_deleted_note_p = true;
+ if (!rtx_equal_p (operands[0], operands[1]))
+ {
+ emit_move_insn (operands[0], operands[1]);
+ emit_insn_deleted_note_p = false;
+ }
if (operands[5] != const0_rtx)
- ix86_expand_binary_operator (PLUS, <MODE>mode, &operands[3]);
+ ix86_expand_binary_operator (PLUS, <MODE>mode, &operands[3],
+ TARGET_APX_NDD);
else if (!rtx_equal_p (operands[3], operands[4]))
emit_move_insn (operands[3], operands[4]);
- else
+ else if (emit_insn_deleted_note_p)
emit_note (NOTE_INSN_DELETED);
DONE;
}
-})
+}
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
(define_insn_and_split "*add<dwi>3_doubleword_zext"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o")
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=r,o,&r,&r")
(plus:<DWI>
(zero_extend:<DWI>
- (match_operand:DWIH 2 "nonimmediate_operand" "rm,r"))
- (match_operand:<DWI> 1 "nonimmediate_operand" "0,0")))
+ (match_operand:DWIH 2 "nonimmediate_operand" "rm,r,rm,r"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "0,0,r,m")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (UNKNOWN, <DWI>mode, operands)"
+ "ix86_binary_operator_ok (UNKNOWN, <DWI>mode, operands,
+ TARGET_APX_NDD)"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
@@ -6352,7 +6362,8 @@ (define_insn_and_split "*add<dwi>3_doubleword_zext"
(match_dup 4))
(const_int 0)))
(clobber (reg:CC FLAGS_REG))])]
- "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[3]);")
+ "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[3]);"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
(define_insn_and_split "*add<dwi>3_doubleword_concat"
[(set (match_operand:<DWI> 0 "register_operand" "=&r")
@@ -7414,14 +7425,14 @@ (define_insn_and_split "*addv<dwi>4_doubleword"
(eq:CCO
(plus:<QPWI>
(sign_extend:<QPWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r"))
(sign_extend:<QPWI>
- (match_operand:<DWI> 2 "nonimmediate_operand" "r,o")))
+ (match_operand:<DWI> 2 "nonimmediate_operand" "r,o,r,o")))
(sign_extend:<QPWI>
(plus:<DWI> (match_dup 1) (match_dup 2)))))
- (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
+ (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
(plus:<DWI> (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
@@ -7451,22 +7462,23 @@ (define_insn_and_split "*addv<dwi>4_doubleword"
(match_dup 5)))])]
{
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
-})
+}
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
(define_insn_and_split "*addv<dwi>4_doubleword_1"
[(set (reg:CCO FLAGS_REG)
(eq:CCO
(plus:<QPWI>
(sign_extend:<QPWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0"))
- (match_operand:<QPWI> 3 "const_scalar_int_operand" "n"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,rm"))
+ (match_operand:<QPWI> 3 "const_scalar_int_operand" "n,n"))
(sign_extend:<QPWI>
(plus:<DWI>
(match_dup 1)
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "<di>")))))
- (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand"
"<di>,<di>")))))
+ (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,&r")
(plus:<DWI> (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)
&& CONST_SCALAR_INT_P (operands[2])
&& rtx_equal_p (operands[2], operands[3])"
"#"
@@ -7500,11 +7512,14 @@ (define_insn_and_split "*addv<dwi>4_doubleword_1"
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
if (operands[2] == const0_rtx)
{
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
emit_insn (gen_addv<mode>4_1 (operands[3], operands[4], operands[5],
operands[5]));
DONE;
}
-})
+}
+[(set_attr "isa" "*,apx_ndd")])
(define_insn "*addv<mode>4_overflow_1"
[(set (reg:CCO FLAGS_REG)
@@ -7514,9 +7529,9 @@ (define_insn "*addv<mode>4_overflow_1"
(match_operator:<DWI> 4 "ix86_carry_flag_operator"
[(match_operand 3 "flags_reg_operand") (const_int 0)])
(sign_extend:<DWI>
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0")))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0,rm,r")))
(sign_extend:<DWI>
- (match_operand:SWI 2 "<general_sext_operand>" "rWe,m")))
+ (match_operand:SWI 2 "<general_sext_operand>" "rWe,m,rWe,m")))
(sign_extend:<DWI>
(plus:SWI
(plus:SWI
@@ -7524,15 +7539,20 @@ (define_insn "*addv<mode>4_overflow_1"
[(match_dup 3) (const_int 0)])
(match_dup 1))
(match_dup 2)))))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=rm,r")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=rm,r,r,r")
(plus:SWI
(plus:SWI
(match_op_dup 5 [(match_dup 3) (const_int 0)])
(match_dup 1))
(match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
- "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_insn "*addv<mode>4_overflow_2"
@@ -7543,26 +7563,29 @@ (define_insn "*addv<mode>4_overflow_2"
(match_operator:<DWI> 4 "ix86_carry_flag_operator"
[(match_operand 3 "flags_reg_operand") (const_int 0)])
(sign_extend:<DWI>
- (match_operand:SWI 1 "nonimmediate_operand" "%0")))
- (match_operand:<DWI> 6 "const_int_operand" "n"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,rm")))
+ (match_operand:<DWI> 6 "const_int_operand" "n,n"))
(sign_extend:<DWI>
(plus:SWI
(plus:SWI
(match_operator:SWI 5 "ix86_carry_flag_operator"
[(match_dup 3) (const_int 0)])
(match_dup 1))
- (match_operand:SWI 2 "x86_64_immediate_operand" "e")))))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=rm")
+ (match_operand:SWI 2 "x86_64_immediate_operand" "e,e")))))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=rm,r")
(plus:SWI
(plus:SWI
(match_op_dup 5 [(match_dup 3) (const_int 0)])
(match_dup 1))
(match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)
&& CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == INTVAL (operands[6])"
- "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "@
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")
(set (attr "length_immediate")
(if_then_else (match_test "IN_RANGE (INTVAL (operands[2]), -128, 127)")
@@ -8384,17 +8407,22 @@ (define_insn "*subsi_3_zext"
;; Add with carry and subtract with borrow
(define_insn "@add<mode>3_carry"
- [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r")
(plus:SWI
(plus:SWI
(match_operator:SWI 4 "ix86_carry_flag_operator"
[(match_operand 3 "flags_reg_operand") (const_int 0)])
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0,rm,r"))
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
- "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "<MODE>")])
@@ -8481,31 +8509,39 @@ (define_insn "*add<mode>3_carry_0r"
(set_attr "mode" "<MODE>")])
(define_insn "*addsi3_carry_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI
(plus:SI
(plus:SI (match_operator:SI 3 "ix86_carry_flag_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 1 "register_operand" "%0"))
- (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
+ (match_operand:SI 1 "nonimmediate_operand" "%0,r,rm"))
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,rBMe,re"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
- "adc{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
+ "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands,
+ TARGET_APX_NDD)"
+ "@
+ adc{l}\t{%2, %k0|%k0, %2}
+ adc{l}\t{%2, %1, %k0|%k0, %1, %2}
+ adc{l}\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
(define_insn "*addsi3_carry_zext_0"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(plus:SI (match_operator:SI 2 "ix86_carry_flag_operator"
[(reg FLAGS_REG) (const_int 0)])
- (match_operand:SI 1 "register_operand" "0"))))
+ (match_operand:SI 1 "nonimmediate_operand" "0,rm"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT"
- "adc{l}\t{$0, %k0|%k0, 0}"
- [(set_attr "type" "alu")
+ "@
+ adc{l}\t{$0, %k0|%k0, 0}
+ adc{l}\t{$0, %1, %k0|%k0, %1, 0}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "SI")])
@@ -8534,20 +8570,25 @@ (define_insn "addcarry<mode>"
(plus:SWI48
(match_operator:SWI48 5 "ix86_carry_flag_operator"
[(match_operand 3 "flags_reg_operand") (const_int 0)])
- (match_operand:SWI48 1 "nonimmediate_operand" "%0,0"))
- (match_operand:SWI48 2 "nonimmediate_operand" "r,rm")))
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,rm,r"))
+ (match_operand:SWI48 2 "nonimmediate_operand" "r,rm,r,m")))
(plus:<DWI>
(zero_extend:<DWI> (match_dup 2))
(match_operator:<DWI> 4 "ix86_carry_flag_operator"
[(match_dup 3) (const_int 0)]))))
- (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r")
(plus:SWI48 (plus:SWI48 (match_op_dup 5
[(match_dup 3) (const_int 0)])
(match_dup 1))
(match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
- "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)"
+ "@
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "<MODE>")])
@@ -8705,7 +8746,8 @@ (define_expand "addcarry<mode>_0"
(match_dup 1)))
(set (match_operand:SWI48 0 "nonimmediate_operand")
(plus:SWI48 (match_dup 1) (match_dup 2)))])]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)")
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands,
+ TARGET_APX_NDD)")
(define_insn "*addcarry<mode>_1"
[(set (reg:CCC FLAGS_REG)
@@ -8715,18 +8757,18 @@ (define_insn "*addcarry<mode>_1"
(plus:SWI48
(match_operator:SWI48 5 "ix86_carry_flag_operator"
[(match_operand 3 "flags_reg_operand") (const_int 0)])
- (match_operand:SWI48 1 "nonimmediate_operand" "%0"))
- (match_operand:SWI48 2 "x86_64_immediate_operand" "e")))
+ (match_operand:SWI48 1 "nonimmediate_operand" "%0,rm"))
+ (match_operand:SWI48 2 "x86_64_immediate_operand" "e,e")))
(plus:<DWI>
(match_operand:<DWI> 6 "const_scalar_int_operand")
(match_operator:<DWI> 4 "ix86_carry_flag_operator"
[(match_dup 3) (const_int 0)]))))
- (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
+ (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r")
(plus:SWI48 (plus:SWI48 (match_op_dup 5
[(match_dup 3) (const_int 0)])
(match_dup 1))
(match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)
&& CONST_INT_P (operands[2])
/* Check that operands[6] is operands[2] zero extended from
<MODE>mode to <DWI>mode. */
@@ -8739,8 +8781,11 @@ (define_insn "*addcarry<mode>_1"
&& ((unsigned HOST_WIDE_INT) CONST_WIDE_INT_ELT (operands[6], 0)
== UINTVAL (operands[2]))
&& CONST_WIDE_INT_ELT (operands[6], 1) == 0))"
- "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "@
+ adc{<imodesuffix>}\t{%2, %0|%0, %2}
+ adc{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "use_carry" "1")
(set_attr "pent_pair" "pu")
(set_attr "mode" "<MODE>")
@@ -9388,12 +9433,12 @@ (define_insn_and_split
"*add<dwi>3_doubleword_cc_overflow_1"
[(set (reg:CCC FLAGS_REG)
(compare:CCC
(plus:<DWI>
- (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0")
- (match_operand:<DWI> 2 "x86_64_hilo_general_operand" "r<di>,o"))
+ (match_operand:<DWI> 1 "nonimmediate_operand" "%0,0,ro,r")
+ (match_operand:<DWI> 2 "x86_64_hilo_general_operand"
"r<di>,o,r<di>,o"))
(match_dup 1)))
- (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
+ (set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r,&r,&r")
(plus:<DWI> (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (PLUS, <DWI>mode, operands)"
+ "ix86_binary_operator_ok (PLUS, <DWI>mode, operands, TARGET_APX_NDD)"
"#"
"&& reload_completed"
[(parallel [(set (reg:CCC FLAGS_REG)
@@ -9422,6 +9467,8 @@ (define_insn_and_split
"*add<dwi>3_doubleword_cc_overflow_1"
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
if (operands[2] == const0_rtx)
{
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
emit_insn (gen_addcarry<mode>_0 (operands[3], operands[4], operands[5]));
DONE;
}
@@ -9430,7 +9477,8 @@ (define_insn_and_split
"*add<dwi>3_doubleword_cc_overflow_1"
operands[5], <MODE>mode);
else
operands[6] = gen_rtx_ZERO_EXTEND (<DWI>mode, operands[5]);
-})
+}
+[(set_attr "isa" "*,*,apx_ndd,apx_ndd")])
;; x == 0 with zero flag test can be done also as x < 1U with carry flag
;; test, where the latter is preferrable if we have some carry consuming
@@ -9445,7 +9493,7 @@ (define_insn_and_split "*add<mode>3_eq"
(match_operand:SWI 1 "nonimmediate_operand"))
(match_operand:SWI 2 "<general_operand>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands, TARGET_APX_NDD)
&& ix86_pre_reload_split ()"
"#"
"&& 1"
@@ -9469,7 +9517,8 @@ (define_insn_and_split "*add<mode>3_ne"
"CONST_INT_P (operands[2])
&& (<MODE>mode != DImode
|| INTVAL (operands[2]) != HOST_WIDE_INT_C (-0x80000000))
- && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)
+ && ix86_binary_operator_ok (PLUS, <MODE>mode, operands,
+ TARGET_APX_NDD)
&& ix86_pre_reload_split ()"
"#"
"&& 1"
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
b/gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
new file mode 100644
index 00000000000..9d5991457da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd-adc.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { int128 && { ! ia32 } } } } */
+/* { dg-options "-mapxf -O2" } */
+
+#include "pr91681-1.c"
+// *addti3_doubleword
+// *addti3_doubleword_zext
+// *adddi3_cc_overflow_1
+// *adddi3_carry
+
+int foo3 (int *a, int b)
+{
+ int c = *a + b + (a > b); /* { dg-warning "comparison between pointer and
integer" } */
+ return c;
+}
+/* { dg-final { scan-assembler-not "xor" } } */
--
2.31.1
