This patch copies the vector reservations from generic-ooo.md and inserts them into generic.md and sifive.md. The vector pipelines are necessary to avoid an ICE from the assert
gcc/ChangeLog: * config/riscv/generic-ooo.md: syntax * config/riscv/generic.md (pipe0): new reservation (generic_vec_load): ditto (generic_vec_store): ditto (generic_vec_loadstore_seg): ditto (generic_generic_vec_alu): ditto (generic_vec_fcmp): ditto (generic_vec_imul): ditto (generic_vec_fadd): ditto (generic_vec_fmul): ditto (generic_crypto): ditto (generic_vec_perm): ditto (generic_vec_reduction): ditto (generic_vec_ordered_reduction): ditto (generic_vec_idiv): ditto (generic_vec_float_divsqrt): ditto (generic_vec_mask): ditto (generic_vec_vesetvl): ditto (generic_vec_setrm): ditto (generic_vec_readlen): ditto * config/riscv/sifive-7.md (sifive_7): new reservation (sifive_7_vec_load): ditto (sifive_7_vec_store): ditto (sifive_7_vec_loadstore_seg): ditto (sifive_7_sifive_7_vec_alu): ditto (sifive_7_vec_fcmp): ditto (sifive_7_vec_imul): ditto (sifive_7_vec_fadd): ditto (sifive_7_vec_fmul): ditto (sifive_7_crypto): ditto (sifive_7_vec_perm): ditto (sifive_7_vec_reduction): ditto (sifive_7_vec_ordered_reduction): ditto (sifive_7_vec_idiv): ditto (sifive_7_vec_float_divsqrt): ditto (sifive_7_vec_mask): ditto (sifive_7_vec_vesetvl): ditto (sifive_7_vec_setrm): ditto (sifive_7_vec_readlen): ditto Signed-off-by: Edwin Lu <e...@rivosinc.com> Co-authored-by: Robin Dapp <rdapp....@gmail.com> --- gcc/config/riscv/generic-ooo.md | 19 ++--- gcc/config/riscv/generic.md | 118 ++++++++++++++++++++++++++++++++ gcc/config/riscv/sifive-7.md | 118 ++++++++++++++++++++++++++++++++ 3 files changed, 242 insertions(+), 13 deletions(-) diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index de93245f965..18b606bb981 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -106,16 +106,14 @@ (define_insn_reservation "generic_ooo_vec_store" 6 ;; Vector segment loads/stores. (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ - vssegte,vssegts,vssegtux,vssegtox")) + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vssegte,vssegts,vssegtux,vssegtox")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Generic integer instructions. (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ - move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,cbo,mvpair,zicond")) + (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,cbo,mvpair,zicond")) "generic_ooo_issue,generic_ooo_ixu_alu") (define_insn_reservation "generic_ooo_sfb_alu" 2 @@ -193,16 +191,13 @@ (define_insn_reservation "generic_ooo_popcount" 2 ;; Regular vector operations and integer comparisons. (define_insn_reservation "generic_ooo_vec_alu" 3 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float comparison, conversion etc. (define_insn_reservation "generic_ooo_vec_fcmp" 3 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ - vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ - vfncvtftoi,vfncvtftof")) + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector integer multiplication. @@ -232,8 +227,7 @@ (define_insn_reservation "generic_ooo_crypto" 4 ;; Vector permute. (define_insn_reservation "generic_ooo_perm" 3 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ - vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector reduction. @@ -265,8 +259,7 @@ (define_insn_reservation "generic_ooo_vec_float_divsqrt" 16 ;; Vector mask operations. (define_insn_reservation "generic_ooo_vec_mask" 2 (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ - vfmovvf,vfmovfv")) + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector vsetvl. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index 3e49d942495..7ac974ad634 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -25,6 +25,15 @@ (define_cpu_unit "alu" "pipe0") (define_cpu_unit "imuldiv" "pipe0") (define_cpu_unit "fdivsqrt" "pipe0") +;; Separate issue queue for vector instructions. +(define_cpu_unit "generic_vec_issue" "pipe0") + +;; Vector alu unit +(define_cpu_unit "generic_vec_alu" "pipe0") + +;; Vector mult/div/sqrt unit +(define_cpu_unit "generic_vec_multi" "pipe0") + (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond")) @@ -93,3 +102,112 @@ (define_insn_reservation "generic_fsqrt" 25 (and (eq_attr "tune" "generic") (eq_attr "type" "fsqrt")) "fdivsqrt*25") + +;; Vector load/store +(define_insn_reservation "generic_vec_load" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,rdfrm")) + "generic_vec_issue,generic_vec_alu") + +(define_insn_reservation "generic_vec_store" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) + "generic_vec_issue,generic_vec_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "generic_vec_loadstore_seg" 10 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vssegte,vssegts,vssegtux,vssegtox")) + "generic_vec_issue,generic_vec_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "generic_generic_vec_alu" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) + "generic_vec_issue,generic_vec_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "generic_vec_fcmp" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof")) + "generic_vec_issue,generic_vec_alu") + +;; Vector integer multiplication. +(define_insn_reservation "generic_vec_imul" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul")) + "generic_vec_issue,generic_vec_alu") + +;; Vector float addition. +(define_insn_reservation "generic_vec_fadd" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfalu,vfwalu")) + "generic_vec_issue,generic_vec_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "generic_vec_fmul" 6 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) + "generic_vec_issue,generic_vec_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "generic_crypto" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "crypto")) + "generic_vec_issue,generic_vec_alu") + +;; Vector permute. +(define_insn_reservation "generic_vec_perm" 3 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) + "generic_vec_issue,generic_vec_alu") + +;; Vector reduction. +(define_insn_reservation "generic_vec_reduction" 8 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vired,viwred,vfredu,vfwredu")) + "generic_vec_issue,generic_vec_multi") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "generic_vec_ordered_reduction" 10 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfredo,vfwredo")) + "generic_vec_issue,generic_vec_multi*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "generic_vec_idiv" 16 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vidiv")) + "generic_vec_issue,generic_vec_multi*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "generic_vec_float_divsqrt" 16 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vfdiv,vfsqrt")) + "generic_vec_issue,generic_vec_multi*3") + +;; Vector mask operations. +(define_insn_reservation "generic_vec_mask" 2 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv")) + "generic_vec_issue,generic_vec_alu") + +;; Vector vsetvl. +(define_insn_reservation "generic_vec_vesetvl" 1 + (and (eq_attr "tune" "generic") + (eq_attr "type" "vsetvl,vsetvl_pre")) + "generic_vec_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "generic_vec_setrm" 20 + (and (eq_attr "tune" "generic") + (eq_attr "type" "wrvxrm,wrfrm")) + "generic_vec_issue,generic_vec_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "generic_vec_readlen" 4 + (and (eq_attr "tune" "generic") + (eq_attr "type" "rdvlenb,rdvl")) + "generic_vec_issue,generic_vec_issue") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index 65d27cf6dc9..bb71d1c5207 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -12,6 +12,15 @@ (define_cpu_unit "sifive_7_B" "sifive_7") (define_cpu_unit "sifive_7_idiv" "sifive_7") (define_cpu_unit "sifive_7_fpu" "sifive_7") +;; Separate issue queue for vector instructions. +(define_cpu_unit "sifive_7_vec_issue" "sifive_7") + +;; Vector alu unit +(define_cpu_unit "sifive_7_vec_alu" "sifive_7") + +;; Vector mult/div/sqrt unit +(define_cpu_unit "sifive_7_vec_multi" "sifive_7") + (define_insn_reservation "sifive_7_load" 3 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "load")) @@ -112,6 +121,115 @@ (define_insn_reservation "sifive_7_popcount" 2 (eq_attr "type" "cpop,clmul")) "sifive_7_A") +;; Vector load/store +(define_insn_reservation "sifive_7_vec_load" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr,rdfrm")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +(define_insn_reservation "sifive_7_vec_store" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "sifive_7_vec_loadstore_seg" 10 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vssegte,vssegts,vssegtux,vssegtox")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "sifive_7_sifive_7_vec_alu" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "sifive_7_vec_fcmp" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector integer multiplication. +(define_insn_reservation "sifive_7_vec_imul" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector float addition. +(define_insn_reservation "sifive_7_vec_fadd" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfalu,vfwalu")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "sifive_7_vec_fmul" 6 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "sifive_7_crypto" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "crypto")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector permute. +(define_insn_reservation "sifive_7_vec_perm" 3 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector reduction. +(define_insn_reservation "sifive_7_vec_reduction" 8 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vired,viwred,vfredu,vfwredu")) + "sifive_7_vec_issue,sifive_7_vec_multi") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "sifive_7_vec_ordered_reduction" 10 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfredo,vfwredo")) + "sifive_7_vec_issue,sifive_7_vec_multi*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "sifive_7_vec_idiv" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vidiv")) + "sifive_7_vec_issue,sifive_7_vec_multi*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "sifive_7_vec_float_divsqrt" 16 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vfdiv,vfsqrt")) + "sifive_7_vec_issue,sifive_7_vec_multi*3") + +;; Vector mask operations. +(define_insn_reservation "sifive_7_vec_mask" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv")) + "sifive_7_vec_issue,sifive_7_vec_alu") + +;; Vector vsetvl. +(define_insn_reservation "sifive_7_vec_vesetvl" 1 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "vsetvl,vsetvl_pre")) + "sifive_7_vec_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "sifive_7_vec_setrm" 20 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "wrvxrm,wrfrm")) + "sifive_7_vec_issue,sifive_7_vec_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "sifive_7_vec_readlen" 4 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "rdvlenb,rdvl")) + "sifive_7_vec_issue,sifive_7_vec_issue") + (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu" "sifive_7_alu,sifive_7_branch") -- 2.34.1