On Fri, Dec 15, 2023 at 1:38 PM Jeff Law <jeffreya...@gmail.com> wrote: > > > > On 12/12/23 20:54, Palmer Dabbelt wrote: > > I can't actually find anything in the ISA manual that makes Ztso imply > > A. In theory the memory ordering is just a different thing that the set > > of availiable instructions (ie, Ztso without A would still imply TSO for > > loads and stores). It also seems like a configuration that could be > > sane to build: without A it's all but impossible to write any meaningful > > multi-core code, and TSO is really cheap for a single core. > > > > That said, I think it's kind of reasonable to provide A to users asking > > for Ztso. So maybe even if this was a mistake it's the right thing to > > do? > > > > gcc/ChangeLog: > > > > * common/config/riscv/riscv-common.cc (riscv_implied_info): > > Remove {"ztso", "a"}. > I'd tend to think step #1 is to determine what the ISA intent is, > meaning engagement with RVI. > > We've got time for that engagement and to adjust based on the result. > So I'd tend to defer until we know if Ztso should imply A or not.
Palmer is correct. There is no coupling between Ztso and A. (And there are uncontrived examples of such systems: e.g. embedded processors without caches that don't support the LR/SC instructions, but happen to be TSO.) > > jeff