Thanks all for comments, will have a try for riscv_v and send V2 if everything goes well.
Pan From: 钟居哲 <[email protected]> Sent: Friday, December 22, 2023 6:44 AM To: Jeff Law <[email protected]>; Li, Pan2 <[email protected]>; gcc-patches <[email protected]> Cc: Wang, Yanzhang <[email protected]>; kito.cheng <[email protected]>; richard.guenther <[email protected]>; Tamar Christina <[email protected]> Subject: Re: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV Maybe use riscv_v ? ________________________________ [email protected]<mailto:[email protected]> From: Jeff Law<mailto:[email protected]> Date: 2023-12-22 03:16 To: pan2.li<mailto:[email protected]>; gcc-patches<mailto:[email protected]> CC: juzhe.zhong<mailto:[email protected]>; yanzhang.wang<mailto:[email protected]>; kito.cheng<mailto:[email protected]>; richard.guenther<mailto:[email protected]>; tamar.christina<mailto:[email protected]> Subject: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV On 12/20/23 19:25, [email protected]<mailto:[email protected]> wrote: > From: Pan Li <[email protected]<mailto:[email protected]>> > > This patch would like to XFail the signbit-5 run test case for > the RVV. Given the case has one limitation like "This test does not > work when the truth type does not match vector type." in the beginning > of the test file. Aka, the RVV vector truth type is not integer type. > > The target board of riscv-sim like below will pick up `-march=rv64gcv` > when building the run test elf. Thus, the RVV cannot bypass this test > case like aarch64_sve with additional option `-march=armv8-a`. > > riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow > > For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`. But isn't that just going to turn this into an XPASS when vector is not enabled? Looking at a recent rv64gc run of mine: > PASS: gcc.dg/signbit-5.c (test for excess errors) > PASS: gcc.dg/signbit-5.c execution test Ideally we'd find a way to handle with and without vector. jeff
