On 1/18/24 09:39, Mikael Pettersson wrote:
When generating RMW logical operations on m68k, the backend
recognizes single-bit operations and rewrites them as bit
instructions on operands adjusted to address the intended byte.
When offsetting the addresses the backend keeps the modes as
SImode, even though the actual access will be in QImode.
The uclinux target defines M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
which adds a check that the adjusted operand is within the bounds
of the original object. Since the address has been offset it is
not, and the compiler ICEs.
The bug is that the modes of the adjusted operands should have been
narrowed to QImode, which is that this patch does. Nearby code
which narrows to HImode gets that right.
Bootstrapped and regression tested on m68k-linux-gnu.
Ok for master? (Note: I don't have commit rights.)
gcc/
PR target/108640
* config/m68k/m68k.cc (output_andsi3): Use QImode for
address adjusted for 1-byte RMW access.
(output_iorsi3): Likewise.
(output_xorsi3): Likewise.
gcc/testsuite/
PR target/108640
* gcc.target/m68k/pr108640.c: New test.
While not really a regression, this can clearly only affect the m68k
target and fixes an ICE. So I went ahead and pushed it to the trunk.
Just a note for the future, the test really isn't m68k specific in that
it should compile just fine on any target GCC supports. It just
happened to ICE on the m68k. We generally prefer to put such tests in
target independent directories. dg-torture, c-torture would be better
choices for this kind of test in the future.
Thanks.
Jeff
