With the release of Binutils 2.42, this brings the level of
system-register support in GCC in line with the current
state-of-the-art in Binutils, ensuring everything available in
Binutils is plainly accessible from GCC.
Where Binutils uses a more detailed description of which features are
responsible for enabling a given system register, GCC aliases the
binutils-equivalent feature flag macro constant to that of the base
architecture implementing the feature, resulting in entries such as
#define AARCH64_FL_S2PIE AARCH64_FL_V8_9A
in `aarch64.h', thus ensuring that the Binutils `aarch64-sys-regs.def'
file can be understood by GCC without the need for modification.
To accompany the addition of the new system registers, a new test is
added confirming they were successfully added to the list of
recognized registers.
gcc/ChangeLog:
* gcc/config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
* /config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
(AARCH64_FL_DEBUGv8p9): Likewise.
(AARCH64_FL_FGT2): Likewise.Likewise.
(AARCH64_FL_ITE): Likewise.
(AARCH64_FL_PFAR): Likewise.
(AARCH64_FL_PMUv3_ICNTR): Likewise.
(AARCH64_FL_PMUv3_SS): Likewise.
(AARCH64_FL_PMUv3p9): Likewise.
(AARCH64_FL_RASv2): Likewise.
(AARCH64_FL_S1PIE): Likewise.
(AARCH64_FL_S1POE): Likewise.
(AARCH64_FL_S2PIE): Likewise.
(AARCH64_FL_S2POE): Likewise.
(AARCH64_FL_SCTLR2): Likewise.
(AARCH64_FL_SEBEP): Likewise.
(AARCH64_FL_SPE_FDS): Likewise.
(AARCH64_FL_TCR2): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/rwsr-armv8p9.c: New.
---
gcc/config/aarch64/aarch64-sys-regs.def | 85 ++++++++++++++++
gcc/config/aarch64/aarch64.h | 20 ++++
.../gcc.target/aarch64/acle/rwsr-armv8p9.c | 99 +++++++++++++++++++
3 files changed, 204 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
diff --git a/gcc/config/aarch64/aarch64-sys-regs.def
b/gcc/config/aarch64/aarch64-sys-regs.def
index fffc35f72c8..6a948171d6e 100644
--- a/gcc/config/aarch64/aarch64-sys-regs.def
+++ b/gcc/config/aarch64/aarch64-sys-regs.def
@@ -54,6 +54,10 @@
SYSREG ("amair_el12", CPENC (3,5,10,3,0), F_ARCHEXT,
AARCH64_FEATURE (V8_1A))
SYSREG ("amair_el2", CPENC (3,4,10,3,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("amair_el3", CPENC (3,6,10,3,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("amair2_el1", CPENC (3,0,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el12", CPENC (3,5,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el2", CPENC (3,4,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el3", CPENC (3,6,10,3,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
SYSREG ("amcfgr_el0", CPENC (3,3,13,2,1),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("amcg1idr_el0", CPENC (3,3,13,2,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
SYSREG ("amcgcr_el0", CPENC (3,3,13,2,2),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
@@ -400,6 +404,7 @@
SYSREG ("erxaddr_el1", CPENC (3,0,5,4,3), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxctlr_el1", CPENC (3,0,5,4,1), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxfr_el1", CPENC (3,0,5,4,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (RAS))
+ SYSREG ("erxgsr_el1", CPENC (3,0,5,3,2),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (RASv2))
SYSREG ("erxmisc0_el1", CPENC (3,0,5,5,0), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxmisc1_el1", CPENC (3,0,5,5,1), F_ARCHEXT,
AARCH64_FEATURE (RAS))
SYSREG ("erxmisc2_el1", CPENC (3,0,5,5,2), F_ARCHEXT,
AARCH64_FEATURE (RAS))
@@ -438,10 +443,14 @@
SYSREG ("hcr_el2", CPENC (3,4,1,1,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("hcrx_el2", CPENC (3,4,1,2,2), F_ARCHEXT,
AARCH64_FEATURE (V8_7A))
SYSREG ("hdfgrtr_el2", CPENC (3,4,3,1,4), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgrtr2_el2", CPENC (3,4,3,1,0), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hdfgwtr_el2", CPENC (3,4,3,1,5), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hdfgwtr2_el2", CPENC (3,4,3,1,1), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hfgitr_el2", CPENC (3,4,1,1,6), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
SYSREG ("hfgrtr_el2", CPENC (3,4,1,1,4), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hfgrtr2_el2", CPENC (3,4,3,1,2), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hfgwtr_el2", CPENC (3,4,1,1,5), F_ARCHEXT,
AARCH64_FEATURE (V8_6A))
+ SYSREG ("hfgwtr2_el2", CPENC (3,4,3,1,3), F_ARCHEXT,
AARCH64_FEATURE (FGT2))
SYSREG ("hpfar_el2", CPENC (3,4,6,0,4), 0,
AARCH64_NO_FEATURES)
SYSREG ("hstr_el2", CPENC (3,4,1,1,3), 0,
AARCH64_NO_FEATURES)
SYSREG ("icc_ap0r0_el1", CPENC (3,0,12,8,4), 0,
AARCH64_NO_FEATURES)
@@ -515,6 +524,8 @@
SYSREG ("id_aa64mmfr0_el1", CPENC (3,0,0,7,0), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr1_el1", CPENC (3,0,0,7,1), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr2_el1", CPENC (3,0,0,7,2), F_REG_READ,
AARCH64_NO_FEATURES)
+ SYSREG ("id_aa64mmfr3_el1", CPENC (3,0,0,7,3), F_REG_READ,
AARCH64_NO_FEATURES)
+ SYSREG ("id_aa64mmfr4_el1", CPENC (3,0,0,7,4), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("id_aa64pfr0_el1", CPENC (3,0,0,4,0), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("id_aa64pfr1_el1", CPENC (3,0,0,4,1), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("id_aa64smfr0_el1", CPENC (3,0,0,4,5), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (SME))
@@ -549,12 +560,17 @@
SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT,
AARCH64_FEATURE (V8_1A))
SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT,
AARCH64_FEATURE (AIE))
SYSREG ("mdccint_el1", CPENC (2,0,0,2,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("mdccsr_el0", CPENC (2,3,0,1,0), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("mdcr_el2", CPENC (3,4,1,1,1), 0,
AARCH64_NO_FEATURES)
SYSREG ("mdcr_el3", CPENC (3,6,1,3,1), 0,
AARCH64_NO_FEATURES)
SYSREG ("mdrar_el1", CPENC (2,0,1,0,0), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("mdscr_el1", CPENC (2,0,0,2,2), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("mdselr_el1", CPENC (2,0,0,4,2), F_ARCHEXT,
AARCH64_FEATURE (DEBUGv8p9))
SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), 0,
AARCH64_NO_FEATURES)
SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), 0,
AARCH64_NO_FEATURES)
SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), 0,
AARCH64_NO_FEATURES)
@@ -593,19 +609,31 @@
SYSREG ("oseccr_el1", CPENC (2,0,0,6,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE,
AARCH64_NO_FEATURES)
SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ,
AARCH64_NO_FEATURES)
+ SYSREG ("pir_el1", CPENC (3,0,10,2,3), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el12", CPENC (3,5,10,2,3), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el2", CPENC (3,4,10,2,3), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el3", CPENC (3,6,10,2,3), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el1", CPENC (3,0,10,2,2), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el12", CPENC (3,5,10,2,2), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el2", CPENC (3,4,10,2,2), F_ARCHEXT,
AARCH64_FEATURE (S1PIE))
SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT,
AARCH64_FEATURE (PAN))
SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128,
AARCH64_NO_FEATURES)
+ SYSREG ("pfar_el1", CPENC (3,0,6,0,5), F_ARCHEXT,
AARCH64_FEATURE (PFAR))
+ SYSREG ("pfar_el12", CPENC (3,5,6,0,5), F_ARCHEXT,
AARCH64_FEATURE (PFAR))
+ SYSREG ("pfar_el2", CPENC (3,4,6,0,5), F_ARCHEXT,
AARCH64_FEATURE (PFAR))
SYSREG ("pmbidr_el1", CPENC (3,0,9,10,7),
F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (PROFILE))
SYSREG ("pmblimitr_el1", CPENC (3,0,9,10,0), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmbptr_el1", CPENC (3,0,9,10,1), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmbsr_el1", CPENC (3,0,9,10,3), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmccfiltr_el0", CPENC (3,3,14,15,7), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmccntr_el0", CPENC (3,3,9,13,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("pmccntsvr_el1", CPENC (2,0,14,11,7), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
SYSREG ("pmceid0_el0", CPENC (3,3,9,12,6), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("pmceid1_el0", CPENC (3,3,9,12,7), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("pmcntenclr_el0", CPENC (3,3,9,12,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmcntenset_el0", CPENC (3,3,9,12,1), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmcr_el0", CPENC (3,3,9,12,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("pmecr_el1", CPENC (3,0,9,14,5), F_ARCHEXT,
AARCH64_FEATURE (SEBEP))
SYSREG ("pmevcntr0_el0", CPENC (3,3,14,8,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevcntr10_el0", CPENC (3,3,14,9,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevcntr11_el0", CPENC (3,3,14,9,3), 0,
AARCH64_NO_FEATURES)
@@ -637,6 +665,37 @@
SYSREG ("pmevcntr7_el0", CPENC (3,3,14,8,7), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevcntr8_el0", CPENC (3,3,14,9,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevcntr9_el0", CPENC (3,3,14,9,1), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("pmevcntsvr0_el1", CPENC (2,0,14,8,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr10_el1", CPENC (2,0,14,9,2), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr11_el1", CPENC (2,0,14,9,3), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr12_el1", CPENC (2,0,14,9,4), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr13_el1", CPENC (2,0,14,9,5), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr14_el1", CPENC (2,0,14,9,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr15_el1", CPENC (2,0,14,9,7), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr16_el1", CPENC (2,0,14,10,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr17_el1", CPENC (2,0,14,10,1), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr18_el1", CPENC (2,0,14,10,2), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr19_el1", CPENC (2,0,14,10,3), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr1_el1", CPENC (2,0,14,8,1), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr20_el1", CPENC (2,0,14,10,4), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr21_el1", CPENC (2,0,14,10,5), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr22_el1", CPENC (2,0,14,10,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr23_el1", CPENC (2,0,14,10,7), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr24_el1", CPENC (2,0,14,11,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr25_el1", CPENC (2,0,14,11,1), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr26_el1", CPENC (2,0,14,11,2), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr27_el1", CPENC (2,0,14,11,3), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr28_el1", CPENC (2,0,14,11,4), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr29_el1", CPENC (2,0,14,11,5), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr2_el1", CPENC (2,0,14,8,2), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr30_el1", CPENC (2,0,14,11,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr3_el1", CPENC (2,0,14,8,3), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr4_el1", CPENC (2,0,14,8,4), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr5_el1", CPENC (2,0,14,8,5), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr6_el1", CPENC (2,0,14,8,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr7_el1", CPENC (2,0,14,8,7), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr8_el1", CPENC (2,0,14,9,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
+ SYSREG ("pmevcntsvr9_el1", CPENC (2,0,14,9,1), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
SYSREG ("pmevtyper0_el0", CPENC (3,3,14,12,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevtyper10_el0", CPENC (3,3,14,13,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevtyper11_el0", CPENC (3,3,14,13,3), 0,
AARCH64_NO_FEATURES)
@@ -668,6 +727,10 @@
SYSREG ("pmevtyper7_el0", CPENC (3,3,14,12,7), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevtyper8_el0", CPENC (3,3,14,13,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmevtyper9_el0", CPENC (3,3,14,13,1), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("pmiar_el1", CPENC (3,0,9,14,7), F_ARCHEXT,
AARCH64_FEATURE (SEBEP))
+ SYSREG ("pmicfiltr_el0", CPENC (3,3,9,6,0), F_ARCHEXT,
AARCH64_FEATURE (PMUv3_ICNTR))
+ SYSREG ("pmicntr_el0", CPENC (3,3,9,4,0), F_ARCHEXT,
AARCH64_FEATURE (PMUv3_ICNTR))
+ SYSREG ("pmicntsvr_el1", CPENC (2,0,14,12,0), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
SYSREG ("pmintenclr_el1", CPENC (3,0,9,14,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmintenset_el1", CPENC (3,0,9,14,1), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmmir_el1", CPENC (3,0,9,14,6), F_REG_READ|F_ARCHEXT,
AARCH64_FEATURE (V8_4A))
@@ -676,6 +739,7 @@
SYSREG ("pmscr_el1", CPENC (3,0,9,9,0), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el12", CPENC (3,5,9,9,0), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmscr_el2", CPENC (3,4,9,9,0), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
+ SYSREG ("pmsdsfr_el1", CPENC (3,4,9,10,4), F_ARCHEXT,
AARCH64_FEATURE (SPE_FDS))
SYSREG ("pmselr_el0", CPENC (3,3,9,12,5), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmsevfr_el1", CPENC (3,0,9,9,5), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmsfcr_el1", CPENC (3,0,9,9,4), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
@@ -684,10 +748,18 @@
SYSREG ("pmsirr_el1", CPENC (3,0,9,9,3), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmslatfr_el1", CPENC (3,0,9,9,6), F_ARCHEXT,
AARCH64_FEATURE (PROFILE))
SYSREG ("pmsnevfr_el1", CPENC (3,0,9,9,1), F_ARCHEXT,
AARCH64_FEATURE (V8_7A))
+ SYSREG ("pmsscr_el1", CPENC (3,0,9,13,3), F_ARCHEXT,
AARCH64_FEATURE (PMUv3_SS))
SYSREG ("pmswinc_el0", CPENC (3,3,9,12,4), F_REG_WRITE,
AARCH64_NO_FEATURES)
+ SYSREG ("pmuacr_el1", CPENC (3,0,9,14,4), F_ARCHEXT,
AARCH64_FEATURE (PMUv3p9))
SYSREG ("pmuserenr_el0", CPENC (3,3,9,14,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmxevcntr_el0", CPENC (3,3,9,13,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("pmxevtyper_el0", CPENC (3,3,9,13,1), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("pmzr_el0", CPENC (3,3,9,13,4), F_REG_WRITE|F_ARCHEXT,
AARCH64_FEATURE (PMUv3_ICNTR))
+ SYSREG ("por_el0", CPENC (3,3,10,2,4), F_ARCHEXT,
AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el1", CPENC (3,0,10,2,4), F_ARCHEXT,
AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el12", CPENC (3,5,10,2,4), F_ARCHEXT,
AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el2", CPENC (3,4,10,2,4), F_ARCHEXT,
AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el3", CPENC (3,6,10,2,4), F_ARCHEXT,
AARCH64_FEATURE (S1POE))
SYSREG ("prbar10_el1", CPENC (3,0,6,13,0), F_ARCHEXT,
AARCH64_FEATURE (V8R))
SYSREG ("prbar10_el2", CPENC (3,4,6,13,0), F_ARCHEXT,
AARCH64_FEATURE (V8R))
SYSREG ("prbar11_el1", CPENC (3,0,6,13,4), F_ARCHEXT,
AARCH64_FEATURE (V8R))
@@ -773,6 +845,10 @@
SYSREG ("sctlr_el12", CPENC (3,5,1,0,0), F_ARCHEXT,
AARCH64_FEATURE (V8_1A))
SYSREG ("sctlr_el2", CPENC (3,4,1,0,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("sctlr_el3", CPENC (3,6,1,0,0), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("sctlr2_el1", CPENC (3,0,1,0,3), F_ARCHEXT,
AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el12", CPENC (3,5,1,0,3), F_ARCHEXT,
AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el2", CPENC (3,4,1,0,3), F_ARCHEXT,
AARCH64_FEATURE (SCTLR2))
+ SYSREG ("sctlr2_el3", CPENC (3,6,1,0,3), F_ARCHEXT,
AARCH64_FEATURE (SCTLR2))
SYSREG ("scxtnum_el0", CPENC (3,3,13,0,7), F_ARCHEXT,
AARCH64_FEATURE (SCXTNUM))
SYSREG ("scxtnum_el1", CPENC (3,0,13,0,7), F_ARCHEXT,
AARCH64_FEATURE (SCXTNUM))
SYSREG ("scxtnum_el12", CPENC (3,5,13,0,7), F_ARCHEXT,
AARCH64_FEATURE (SCXTNUM))
@@ -803,11 +879,16 @@
SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("ssbs", CPENC (3,3,4,2,6), F_ARCHEXT,
AARCH64_FEATURE (SSBS))
SYSREG ("svcr", CPENC (3,3,4,2,2), F_ARCHEXT,
AARCH64_FEATURE (SME))
+ SYSREG ("s2pir_el2", CPENC (3,4,10,2,5), F_ARCHEXT,
AARCH64_FEATURE (S2PIE))
+ SYSREG ("s2por_el1", CPENC (3,0,10,2,5), F_ARCHEXT,
AARCH64_FEATURE (S2POE))
SYSREG ("tco", CPENC (3,3,4,2,7), F_ARCHEXT,
AARCH64_FEATURE (MEMTAG))
SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("tcr_el12", CPENC (3,5,2,0,2), F_ARCHEXT,
AARCH64_FEATURE (V8_1A))
SYSREG ("tcr_el2", CPENC (3,4,2,0,2), 0,
AARCH64_NO_FEATURES)
SYSREG ("tcr_el3", CPENC (3,6,2,0,2), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("tcr2_el1", CPENC (3,0,2,0,3), F_ARCHEXT,
AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el12", CPENC (3,5,2,0,3), F_ARCHEXT,
AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el2", CPENC (3,4,2,0,3), F_ARCHEXT,
AARCH64_FEATURE (TCR2))
SYSREG ("teecr32_el1", CPENC (2,2,0,0,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("teehbr32_el1", CPENC (2,2,1,0,0), 0,
AARCH64_NO_FEATURES)
SYSREG ("tfsr_el1", CPENC (3,0,5,6,0), F_ARCHEXT,
AARCH64_FEATURE (MEMTAG))
@@ -944,6 +1025,10 @@
SYSREG ("trcimspec6", CPENC (2,1,0,6,7), 0,
AARCH64_NO_FEATURES)
SYSREG ("trcimspec7", CPENC (2,1,0,7,7), 0,
AARCH64_NO_FEATURES)
SYSREG ("trcitctrl", CPENC (2,1,7,0,4), 0,
AARCH64_NO_FEATURES)
+ SYSREG ("trcitecr_el1", CPENC (3,0,1,2,3), F_ARCHEXT,
AARCH64_FEATURE (ITE))
+ SYSREG ("trcitecr_el12", CPENC (3,5,1,2,3), F_ARCHEXT,
AARCH64_FEATURE (ITE))
+ SYSREG ("trcitecr_el2", CPENC (3,4,1,2,3), F_ARCHEXT,
AARCH64_FEATURE (ITE))
+ SYSREG ("trciteedcr", CPENC (2,1,0,2,1), F_ARCHEXT,
AARCH64_FEATURE (ITE))
SYSREG ("trclar", CPENC (2,1,7,12,6), F_REG_WRITE,
AARCH64_NO_FEATURES)
SYSREG ("trclsr", CPENC (2,1,7,13,6), F_REG_READ,
AARCH64_NO_FEATURES)
SYSREG ("trcoslar", CPENC (2,1,1,0,4), F_REG_WRITE,
AARCH64_NO_FEATURES)
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 157a0b9dfa5..45e901cda64 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -297,6 +297,26 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE =
AARCH64_FL_SM_OFF;
#define AARCH64_FL_SCXTNUM AARCH64_FL_V8_5A
#define AARCH64_FL_ID_PFR2 AARCH64_FL_V8_5A
+/* Armv8.9-A extension feature bits defined in Binutils but absent from GCC,
+ aliased to their base architecture. */
+#define AARCH64_FL_AIE AARCH64_FL_V8_9A
+#define AARCH64_FL_DEBUGv8p9 AARCH64_FL_V8_9A
+#define AARCH64_FL_FGT2 AARCH64_FL_V8_9A
+#define AARCH64_FL_ITE AARCH64_FL_V8_9A
+#define AARCH64_FL_PFAR AARCH64_FL_V8_9A
+#define AARCH64_FL_PMUv3_ICNTR AARCH64_FL_V8_9A
+#define AARCH64_FL_PMUv3_SS AARCH64_FL_V8_9A
+#define AARCH64_FL_PMUv3p9 AARCH64_FL_V8_9A
+#define AARCH64_FL_RASv2 AARCH64_FL_V8_9A
+#define AARCH64_FL_S1PIE AARCH64_FL_V8_9A
+#define AARCH64_FL_S1POE AARCH64_FL_V8_9A
+#define AARCH64_FL_S2PIE AARCH64_FL_V8_9A
+#define AARCH64_FL_S2POE AARCH64_FL_V8_9A
+#define AARCH64_FL_SCTLR2 AARCH64_FL_V8_9A
+#define AARCH64_FL_SEBEP AARCH64_FL_V8_9A
+#define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A
+#define AARCH64_FL_TCR2 AARCH64_FL_V8_9A
+
/* SHA2 is an optional extension to AdvSIMD. */
#define TARGET_SHA2 (AARCH64_ISA_SHA2)
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
new file mode 100644
index 00000000000..e2f297bbeeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-armv8p9.c
@@ -0,0 +1,99 @@
+/* Ensure support is present for all armv8.9-a system registers. */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.9-a" } */
+#include <arm_acle.h>
+void
+readwrite_armv8p9a_sysregs ()
+{
+ long long int a;
+
+ /* Write-only system registers. */
+ __arm_wsr64 ("pmzr_el0", a); /* { dg-final { scan-assembler
"msr\ts3_3_c9_c13_4, x0" } } */
+
+ /* Read/write or write-only system registers. */
+ a = __arm_rsr64 ("amair2_el1"); /* { { dg-final {
scan-assembler "s3_0_c10_c3_1" } } */
+ a = __arm_rsr64 ("amair2_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c10_c3_1" } } */
+ a = __arm_rsr64 ("amair2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c3_1" } } */
+ a = __arm_rsr64 ("amair2_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_6_c10_c3_1" } } */
+ a = __arm_rsr64 ("erxgsr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c5_c3_2" } } */
+ a = __arm_rsr64 ("hdfgrtr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c3_c1_0" } } */
+ a = __arm_rsr64 ("hdfgwtr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c3_c1_1" } } */
+ a = __arm_rsr64 ("hfgrtr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c3_c1_2" } } */
+ a = __arm_rsr64 ("hfgwtr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c3_c1_3" } } */
+ a = __arm_rsr64 ("id_aa64mmfr3_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s3_0_c0_c7_3" } } */
+ a = __arm_rsr64 ("id_aa64mmfr4_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s3_0_c0_c7_4" } } */
+ a = __arm_rsr64 ("mair2_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c10_c2_1" } } */
+ a = __arm_rsr64 ("mair2_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c10_c2_1" } } */
+ a = __arm_rsr64 ("mair2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c1_1" } } */
+ a = __arm_rsr64 ("mair2_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_6_c10_c1_1" } } */
+ a = __arm_rsr64 ("mdselr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s2_0_c0_c4_2" } } */
+ a = __arm_rsr64 ("pir_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c10_c2_3" } } */
+ a = __arm_rsr64 ("pir_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c10_c2_3" } } */
+ a = __arm_rsr64 ("pir_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c2_3" } } */
+ a = __arm_rsr64 ("pir_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_6_c10_c2_3" } } */
+ a = __arm_rsr64 ("pire0_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c10_c2_2" } } */
+ a = __arm_rsr64 ("pire0_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c10_c2_2" } } */
+ a = __arm_rsr64 ("pire0_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c2_2" } } */
+ a = __arm_rsr64 ("pfar_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c6_c0_5" } } */
+ a = __arm_rsr64 ("pfar_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c6_c0_5" } } */
+ a = __arm_rsr64 ("pfar_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c6_c0_5" } } */
+ a = __arm_rsr64 ("pmccntsvr_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_7" } } */
+ a = __arm_rsr64 ("pmecr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c9_c14_5" } } */
+ a = __arm_rsr64 ("pmevcntsvr0_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_0" } } */
+ a = __arm_rsr64 ("pmevcntsvr10_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_2" } } */
+ a = __arm_rsr64 ("pmevcntsvr11_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_3" } } */
+ a = __arm_rsr64 ("pmevcntsvr12_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_4" } } */
+ a = __arm_rsr64 ("pmevcntsvr13_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_5" } } */
+ a = __arm_rsr64 ("pmevcntsvr14_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_6" } } */
+ a = __arm_rsr64 ("pmevcntsvr15_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_7" } } */
+ a = __arm_rsr64 ("pmevcntsvr16_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_0" } } */
+ a = __arm_rsr64 ("pmevcntsvr17_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_1" } } */
+ a = __arm_rsr64 ("pmevcntsvr18_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_2" } } */
+ a = __arm_rsr64 ("pmevcntsvr19_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_3" } } */
+ a = __arm_rsr64 ("pmevcntsvr1_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_1" } } */
+ a = __arm_rsr64 ("pmevcntsvr20_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_4" } } */
+ a = __arm_rsr64 ("pmevcntsvr21_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_5" } } */
+ a = __arm_rsr64 ("pmevcntsvr22_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_6" } } */
+ a = __arm_rsr64 ("pmevcntsvr23_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c10_7" } } */
+ a = __arm_rsr64 ("pmevcntsvr24_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_0" } } */
+ a = __arm_rsr64 ("pmevcntsvr25_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_1" } } */
+ a = __arm_rsr64 ("pmevcntsvr26_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_2" } } */
+ a = __arm_rsr64 ("pmevcntsvr27_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_3" } } */
+ a = __arm_rsr64 ("pmevcntsvr28_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_4" } } */
+ a = __arm_rsr64 ("pmevcntsvr29_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_5" } } */
+ a = __arm_rsr64 ("pmevcntsvr2_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_2" } } */
+ a = __arm_rsr64 ("pmevcntsvr30_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c11_6" } } */
+ a = __arm_rsr64 ("pmevcntsvr3_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_3" } } */
+ a = __arm_rsr64 ("pmevcntsvr4_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_4" } } */
+ a = __arm_rsr64 ("pmevcntsvr5_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_5" } } */
+ a = __arm_rsr64 ("pmevcntsvr6_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_6" } } */
+ a = __arm_rsr64 ("pmevcntsvr7_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c8_7" } } */
+ a = __arm_rsr64 ("pmevcntsvr8_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_0" } } */
+ a = __arm_rsr64 ("pmevcntsvr9_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c9_1" } } */
+ a = __arm_rsr64 ("pmiar_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c9_c14_7" } } */
+ a = __arm_rsr64 ("pmicfiltr_el0"); /* { { dg-final { scan-assembler
"mrs\tx0, s3_3_c9_c6_0" } } */
+ a = __arm_rsr64 ("pmicntr_el0"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_3_c9_c4_0" } } */
+ a = __arm_rsr64 ("pmicntsvr_el1"); /* { { dg-final { scan-assembler
"mrs\tx0, s2_0_c14_c12_0" } } */
+ a = __arm_rsr64 ("pmsdsfr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c9_c10_4" } } */
+ a = __arm_rsr64 ("pmsscr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c9_c13_3" } } */
+ a = __arm_rsr64 ("pmuacr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c9_c14_4" } } */
+ a = __arm_rsr64 ("por_el0"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_3_c10_c2_4" } } */
+ a = __arm_rsr64 ("por_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c10_c2_4" } } */
+ a = __arm_rsr64 ("por_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c10_c2_4" } } */
+ a = __arm_rsr64 ("por_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c2_4" } } */
+ a = __arm_rsr64 ("por_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_6_c10_c2_4" } } */
+ a = __arm_rsr64 ("sctlr2_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c1_c0_3" } } */
+ a = __arm_rsr64 ("sctlr2_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c1_c0_3" } } */
+ a = __arm_rsr64 ("sctlr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c1_c0_3" } } */
+ a = __arm_rsr64 ("sctlr2_el3"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_6_c1_c0_3" } } */
+ a = __arm_rsr64 ("s2pir_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c10_c2_5" } } */
+ a = __arm_rsr64 ("s2por_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c10_c2_5" } } */
+ a = __arm_rsr64 ("tcr2_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c2_c0_3" } } */
+ a = __arm_rsr64 ("tcr2_el12"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_5_c2_c0_3" } } */
+ a = __arm_rsr64 ("tcr2_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c2_c0_3" } } */
+ a = __arm_rsr64 ("trcitecr_el1"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_0_c1_c2_3" } } */
+ a = __arm_rsr64 ("trcitecr_el12"); /* { { dg-final { scan-assembler
"mrs\tx0, s3_5_c1_c2_3" } } */
+ a = __arm_rsr64 ("trcitecr_el2"); /* { { dg-final { scan-assembler "mrs\tx0,
s3_4_c1_c2_3" } } */
+ a = __arm_rsr64 ("trciteedcr"); /* { { dg-final { scan-assembler "mrs\tx0,
s2_1_c0_c2_1" } } */
+}
+
--
2.42.0
