Hi,
on 2024/2/26 14:18, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> There is no immediate value splatting instruction in powerpc. Currently that
> needs to be stored in a register or memory. For addressing this I have updated
> the predicate for the second operand in vsx_splat to splat_input_operand,
> which will handle the operands appropriately.
The test case fails with error message with GCC 11, but fails with ICE from GCC
12, it's kind of regression, so I think we can make such fix in this stage.
Out of curiosity, did you check why it triggers error messages on GCC 11? I
guess the difference from GCC 12 is Bill introduced new built-in framework in
GCC12 which adds the support for the bif, but I'm curious what prevent this
being supported before that.
>
> 2024-02-26 Jeevitha Palanisamy <jeevi...@linux.ibm.com>
>
> gcc/
> PR target/113950
> * config/rs6000/vsx.md (vsx_splat_<mode>): Updated the predicates
> for second operand.
>
> gcc/testsuite/
> PR target/113950
> * gcc.target/powerpc/pr113950.c: New testcase.
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 6111cc90eb7..e5688ff972a 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -4660,7 +4660,7 @@
> (define_expand "vsx_splat_<mode>"
> [(set (match_operand:VSX_D 0 "vsx_register_operand")
> (vec_duplicate:VSX_D
> - (match_operand:<VEC_base> 1 "input_operand")))]
> + (match_operand:<VEC_base> 1 "splat_input_operand")))]
> "VECTOR_MEM_VSX_P (<MODE>mode)"
> {
> rtx op1 = operands[1];
This hunk actually does force_reg already:
...
else if (!REG_P (op1))
op1 = force_reg (<VSX_D:VEC_base>mode, op1);
but it's assigning to op1 unexpectedly (an omission IMHO), so just
simply fix it with:
else if (!REG_P (op1))
- op1 = force_reg (<VSX_D:VEC_base>mode, op1);
+ operands[1] = force_reg (<VSX_D:VEC_base>mode, op1);
instead, can you verify?
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
> b/gcc/testsuite/gcc.target/powerpc/pr113950.c
> new file mode 100644
> index 00000000000..29ded29f683
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
> @@ -0,0 +1,24 @@
> +/* PR target/113950 */
> +/* { dg-do compile } */
We need an effective target to ensure vsx support, for now it's powerpc_vsx_ok.
ie: /* { dg-require-effective-target powerpc_vsx_ok } */
(most/all of its uses would be replaced with an enhanced powerpc_vsx in next
stage 1).
BR,
Kewen
> +/* { dg-options "-O1" } */
> +
> +/* Verify we do not ICE on the following. */
> +
> +void abort (void);
> +
> +int main ()
> +{
> + int i;
> + vector signed long long vsll_result, vsll_expected_result;
> + signed long long sll_arg1;
> +
> + sll_arg1 = 300;
> + vsll_expected_result = (vector signed long long) {300, 300};
> + vsll_result = __builtin_vsx_splat_2di (sll_arg1);
> +
> + for (i = 0; i < 2; i++)
> + if (vsll_result[i] != vsll_expected_result[i])
> + abort();
> +
> + return 0;
> +}
>
>
