LGTM. But please commit it with adding [NFC] into the title of this patch:
RISC-V: Refactor expand_vec_cmp [NFC]
------------------ Original ------------------
From: "demin.han"<demin....@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zh...@rivai.ai>;
"kito.cheng"<kito.ch...@gmail.com>; "Li, Pan2"<pan2...@intel.com>;
"jeffreyalaw"<jeffreya...@gmail.com>;
Subject: [PATCH 2/5] RISC-V: Refactor expand_vec_cmp
There are two expand_vec_cmp functions.
They have same structure and similar code.
We can use default arguments instead of overloading.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
* config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
(expand_vec_cmp_float): Adapt arguments
Signed-off-by: demin.han <demin....@starfivetech.com>
---
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 44
+++++++++++----------------------
2 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 80efdf2b7e5..b8735593805 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -603,7 +603,7 @@ bool simm5_p (rtx);
bool neg_simm5_p (rtx);
#ifdef RTX_CODE
bool has_vi_variant_p (rtx_code, rtx);
-void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
+void expand_vec_cmp (rtx, rtx_code, rtx, rtx, rtx = nullptr, rtx = nullptr);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
void expand_cond_len_unop (unsigned, rtx *);
void expand_cond_len_binop (unsigned, rtx *);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0cfbd21ce6f..14e75b9a117 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2752,7 +2752,8 @@ vectorize_related_mode (machine_mode vector_mode,
scalar_mode element_mode,
/* Expand an RVV comparison. */
void
-expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
+expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
+ rtx maskoff)
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
@@ -2762,8 +2763,8 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx
op1)
{
rtx lt = gen_reg_rtx (mask_mode);
rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, op0, op1);
- expand_vec_cmp (gt, GT, op0, op1);
+ expand_vec_cmp (lt, LT, op0, op1, mask,
maskoff);
+ expand_vec_cmp (gt, GT, op0, op1, mask,
maskoff);
icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP,
ops);
@@ -2771,33 +2772,16 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx
op1)
}
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP, ops);
-}
-
-void
-expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0,
- rtx op1)
-{
- machine_mode mask_mode = GET_MODE (target);
- machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
-
- if (code == LTGT)
+ if (!mask && !maskoff)
{
- rtx lt = gen_reg_rtx (mask_mode);
- rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, mask, maskoff, op0,
op1);
- expand_vec_cmp (gt, GT, mask, maskoff, op0,
op1);
- icode = code_for_pred (IOR, mask_mode);
- rtx ops[] = {target, lt, gt};
- emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
- return;
+ rtx ops[] = {target, cmp, op0, op1};
+ emit_vlmax_insn (icode, COMPARE_OP, ops);
+ }
+ else
+ {
+ rtx ops[] = {target, mask, maskoff, cmp, op0,
op1};
+ emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
-
- rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, mask, maskoff, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
/* Expand an RVV floating-point comparison:
@@ -2875,7 +2859,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0,
rtx op1,
else
{
/* vmfeq.vv v0, vb, vb, v0.t */
- expand_vec_cmp (eq0, EQ, eq0, eq0, op1, op1);
+ expand_vec_cmp (eq0, EQ, op1, op1, eq0, eq0);
}
break;
default:
@@ -2893,7 +2877,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0,
rtx op1,
if (code == ORDERED)
emit_move_insn (target, eq0);
else
- expand_vec_cmp (eq0, code, eq0, eq0, op0, op1);
+ expand_vec_cmp (eq0, code, op0, op1, eq0, eq0);
if (can_invert_p)
{
--
2.43.2
