On 3/4/24 11:22 PM, Li, Pan2 wrote:
Thanks Jeff for comments.
But in the case of a vector modes, we can usually reinterpret the
underlying bits in whatever mode we want and do any of the usual
operations on those bits.
Yes, I think that is why we can allow vector mode in get_stored_val if my
understanding is correct.
And then the different modes will return by gen_low_part. Unfortunately, there
are some modes
(less than a vector bit size like V2SF, V2QI for vlen=128) are considered as
invalid by validate_subreg,
and return NULL_RTX result in the final ICE.
That doesn't make a lot of sense to me. Even for vlen=128 I would have
expected that we can still use a subreg to access low bits. After all
we might have had a V16QI vector and done a reduction of some sort
storing the result in the first element and we have to be able to
extract that result and move it around.
I'm not real keen on a target workaround. While extremely safe, I
wouldn't be surprised if other ports could trigger the ICE and we'd end
up patching up multiple targets for what is, IMHO, a more generic issue.
As Richi noted using validate_subreg here isn't great. Does it work to
factor out this code from extract_low_bits:
if (!int_mode_for_mode (src_mode).exists (&src_int_mode)
|| !int_mode_for_mode (mode).exists (&int_mode))
return NULL_RTX;
if (!targetm.modes_tieable_p (src_int_mode, src_mode))
return NULL_RTX;
if (!targetm.modes_tieable_p (int_mode, mode))
return NULL_RTX;
And use that in the condition (and in extract_low_bits rather than
duplicating the code)?
jeff
ps. No need to apologize for the pings. This completely fell off my radar.
