Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.ch...@gmail.com>
Sent: Sunday, March 31, 2024 9:05 AM
To: Li, Pan2 <pan2...@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
<yanzhang.w...@intel.com>
Subject: Re: [PATCH] RISC-V: Fix misspelled term builtin in error message
lgtm
On Sat, Mar 30, 2024 at 8:07 PM <pan2...@intel.com> wrote:
>
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead
> [-Werror=format-diag]
> 4592 | "builtin function %qE requires the V ISA extension",
> exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li <pan2...@intel.com>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c | 2 +-
> .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
> if (!TARGET_VECTOR)
> error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
> return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> ---
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
> size_t test_1 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> ---
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
> size_t
> test_3 (size_t vl)
> {
> - return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> + return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> }
> --
> 2.34.1
>
