Hi,
on 2024/4/12 06:15, Peter Bergner wrote:
> FYI: This patch is an update to Will Schmidt's patches to fix PR101865:
>
> https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601825.html
> https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601823.html
>
> ...taking into consideration patch reviews received than. I also found
> a few more locations that needed patching, as well as simplifying the
> testsuite test cases by removing the need to scan for the predefined macros.
>
>
>
> The bug in PR101865 is the _ARCH_PWR8 predefined macro is conditional upon
> TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the
> -mno-altivec or -mno-vsx options are used. The solution here is to create
> a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of
> Altivec or VSX enablement.
>
> Unfortunately, the only way to create an OPTION_MASK_* mask is to create
> a new option, which we have done here, but marked it as WarnRemoved since
> we do not want users using it. For stage1, we will look into how we can
> create ISA mask flags for use in the compiler without the need for explicit
> options.
>
> The passed bootstrap and regtest on powerpc64le-linux. Ok for trunk?
Thanks for fixing this. I guess it should go well on powerpc64-linux too,
but since it's very late stage4 now, could you also test this on BE machine?
>
> This is also broken on the release branches, so ok for backports after
> some burn-in time on trunk?
>
> Peter
>
>
> 2024-04-11 Will Schmidt <will_schm...@linux.ibm.com>
> Peter Bergner <berg...@linux.ibm.com>
>
> gcc/
> PR target/101865
> * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
> TARGET_POWER8.
> * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
> OPTION_MASK_POWER8.
> * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8.
> (ISA_2_7_MASKS_SERVER): Likewise.
> * config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
> comment. Use OPTION_MASK_POWER8 and TARGET_POWER8.
> * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
> * config/rs6000/rs6000.md (define_attr "isa"): Add p8.
> (define_attr "enabled"): Handle it.
> (define_insn "prefetch"): Use TARGET_POWER8.
> * config/rs6000/rs6000.opt (mdo-not-use-this-option): New.
>
> gcc/testsuite/
> PR target/101865
> * gcc.target/powerpc/predefined-p7-novsx.c: New test.
> * gcc.target/powerpc/predefined-p8-noaltivec-novsx.c: New test.
> * gcc.target/powerpc/predefined-p8-noaltivec.c: New test.
> * gcc.target/powerpc/predefined-p8-novsx.c: New test.
> * gcc.target/powerpc/predefined-p8-pragma-vsx.c: New test.
> * gcc.target/powerpc/predefined-p9-novsx.c: New test.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index e7d6204074c..320affd79e3 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
> fncode)
> case ENB_P7_64:
> return TARGET_POPCNTD && TARGET_POWERPC64;
> case ENB_P8:
> - return TARGET_DIRECT_MOVE;
> + return TARGET_POWER8;
> case ENB_P8V:
> return TARGET_P8_VECTOR;
> case ENB_P9:
> diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
> index 647f20de7f2..bd493ab87c5 100644
> --- a/gcc/config/rs6000/rs6000-c.cc
> +++ b/gcc/config/rs6000/rs6000-c.cc
> @@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT
> flags)
> rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
> if ((flags & OPTION_MASK_POPCNTD) != 0)
> rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
> - if ((flags & OPTION_MASK_P8_VECTOR) != 0)
> + if ((flags & OPTION_MASK_POWER8) != 0)
> rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8");
> if ((flags & OPTION_MASK_MODULO) != 0)
> rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9");
> diff --git a/gcc/config/rs6000/rs6000-cpus.def
> b/gcc/config/rs6000/rs6000-cpus.def
> index 45dd5a85901..6ee678e69c3 100644
> --- a/gcc/config/rs6000/rs6000-cpus.def
> +++ b/gcc/config/rs6000/rs6000-cpus.def
> @@ -47,6 +47,7 @@
> fusion here, instead set it in rs6000.cc if we are tuning for a power8
> system. */
> #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
> + | OPTION_MASK_POWER8 \
> | OPTION_MASK_P8_VECTOR \
> | OPTION_MASK_CRYPTO \
> | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
> @@ -130,6 +131,7 @@
> | OPTION_MASK_MODULO \
> | OPTION_MASK_MULHW \
> | OPTION_MASK_NO_UPDATE \
> + | OPTION_MASK_POWER8 \
> | OPTION_MASK_P8_FUSION \
> | OPTION_MASK_P8_VECTOR \
> | OPTION_MASK_P9_MINMAX \
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index c241371147c..117999613d8 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -3807,11 +3807,10 @@ rs6000_option_override_internal (bool global_init_p)
> "-mmultiple");
> }
>
> - /* If little-endian, default to -mstrict-align on older processors.
> - Testing for direct_move matches power8 and later. */
> + /* If little-endian, default to -mstrict-align on older processors. */
> if (!BYTES_BIG_ENDIAN
> && !(processor_target_table[tune_index].target_enable
> - & OPTION_MASK_P8_VECTOR))
> + & OPTION_MASK_POWER8))
> rs6000_isa_flags |= ~rs6000_isa_flags_explicit &
> OPTION_MASK_STRICT_ALIGN;
>
> /* Add some warnings for VSX. */
> @@ -3897,7 +3896,7 @@ rs6000_option_override_internal (bool global_init_p)
> else
> rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
> }
> - else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
> + else if (TARGET_P8_VECTOR || TARGET_POWER8 || TARGET_CRYPTO)
> rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
> else if (TARGET_VSX)
> rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 77d045c9f6e..2cde2e329b0 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -490,7 +490,7 @@ extern int rs6000_vector_align[];
> memory support. */
> #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
> || TARGET_QUAD_MEMORY_ATOMIC \
> - || TARGET_DIRECT_MOVE)
> + || TARGET_POWER8)
>
> #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
>
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index bc8bc6ab060..ac5651d7420 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -355,7 +355,7 @@ (define_attr "cpu"
> (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
>
> ;; The ISA we implement.
> -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
> +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10"
> (const_string "any"))
>
> ;; Is this alternative enabled for the current CPU/ISA/etc.?
> @@ -380,6 +380,10 @@ (define_attr "enabled" ""
> (match_test "TARGET_VSX"))
> (const_int 1)
>
> + (and (eq_attr "isa" "p8")
> + (match_test "TARGET_POWER8"))
> + (const_int 1)
> +
> (and (eq_attr "isa" "p8v")
> (match_test "TARGET_P8_VECTOR"))
> (const_int 1)
> @@ -14305,7 +14309,7 @@ (define_insn "prefetch"
> AIX does not support the dcbtstt and dcbtt extended mnemonics.
> The AIX assembler does not support the three operand form of dcbt
> and dcbtst on Power 7 (-mpwr7). */
> - int inst_select = INTVAL (operands[2]) || !TARGET_DIRECT_MOVE;
> + int inst_select = INTVAL (operands[2]) || !TARGET_POWER8;
>
> if (REG_P (operands[0]))
> {
> diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
> index dfd5051b964..457c7d05e7e 100644
> --- a/gcc/config/rs6000/rs6000.opt
> +++ b/gcc/config/rs6000/rs6000.opt
> @@ -470,6 +470,10 @@ Save the TOC in the prologue for indirect calls rather
> than inline.
> mvsx-timode
> Target RejectNegative Undocumented Ignore
>
> +;; This option exists only to create its MASK. It is not intended for users.
> +mdo-not-use-this-option
> +Target RejectNegative Mask(POWER8) Var(rs6000_isa_flags) WarnRemoved
> +
I can understand the given name is to avoid users to use it, but it looks odd,
personally
I'm inclined to mpower8 (or even mpower8-internal) even if it's more likely to
be used but
it's a bit more meaningful (especially we already have mpower10), theoretically
speaking
it's undocumented users shouldn't use it at all.
And I think we want explicit "Undocumented" here, and WarnRemoved seems not
suitable here
since it's for some option which worked before but then wasn't supported any
longer, but
this one is new, may be "Warn(Don't use %qs)" instead?
[snip...]
> diff --git a/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c
> b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c
> new file mode 100644
> index 00000000000..cb3cc16d968
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/predefined-p8-pragma-vsx.c
> @@ -0,0 +1,101 @@
> +/* PR target/101865 */
> +/* { dg-do run } */
> +/* { dg-require-effective-target p8vector_hw } */
> +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */
Nit: -O2 looks useless and can be dropped?
The others look good to me, thanks!
BR,
Kewen
> +
> +/* Verify we correctly set our predefined macros in the face of #pragma
> usage. */
> +
> +#include <stdio.h>
> +#include <stdlib.h>
> +
> +volatile int power8_set;
> +volatile int vsx_set;
> +
