Hi Pan,
thanks for working on this.
In general the patch looks reasonable to me but I'd rather
have some more comments about the high-level idea.
E.g. cbranch is implemented like aarch64 by xor'ing the
bitmasks and comparing the result against zero (so we branch
based on mask equality).
> +;; vcond_mask_len
High-level description here instead please.
> +(define_insn_and_split "vcond_mask_len_<mode>"
> + [(set (match_operand:VB 0 "register_operand")
> + (unspec: VB [
> + (match_operand:VB 1 "register_operand")
> + (match_operand:VB 2 "const_1_operand")
I guess it works like that because operand[2] is just implicitly
used anyway but shouldn't that rather be an all_ones_operand?
> + && riscv_vector::get_vector_mode (Pmode, GET_MODE_NUNITS
> (<MODE>mode)).exists ()"
Seems a bit odd on first sight. If all we want to do is to
select between two masks why do we need a large Pmode mode?
> + rtx ops[] = {operands[0], operands[1], operands[1], cmp, reg,
> operands[4]};
So that's basically a mask-move with length? Can't this be done
differently? If not, please describe, maybe this is already
the shortest way.
Regards
Robin
