Thanks for doing this a pre-patch. Minor request below:
Tamar Christina <tamar.christ...@arm.com> writes:
> ;; Perform a logical operation on operands 2 and 3, using operand 1 as
> @@ -6676,38 +6690,42 @@ (define_insn "@aarch64_pred_<optab><mode>_z"
> (define_insn "*<optab><mode>3_cc"
> [(set (reg:CC_NZC CC_REGNUM)
> (unspec:CC_NZC
> - [(match_operand:VNx16BI 1 "register_operand" "Upa")
> + [(match_operand:VNx16BI 1 "register_operand")
> (match_operand 4)
> (match_operand:SI 5 "aarch64_sve_ptrue_flag")
> (and:PRED_ALL
> (LOGICAL:PRED_ALL
> - (match_operand:PRED_ALL 2 "register_operand" "Upa")
> - (match_operand:PRED_ALL 3 "register_operand" "Upa"))
> + (match_operand:PRED_ALL 2 "register_operand")
> + (match_operand:PRED_ALL 3 "register_operand"))
> (match_dup 4))]
> UNSPEC_PTEST))
> - (set (match_operand:PRED_ALL 0 "register_operand" "=Upa")
> + (set (match_operand:PRED_ALL 0 "register_operand")
> (and:PRED_ALL (LOGICAL:PRED_ALL (match_dup 2) (match_dup 3))
> (match_dup 4)))]
> "TARGET_SVE"
> - "<logical>s\t%0.b, %1/z, %2.b, %3.b"
> + {@ [ cons: =0, 1 , 2 , 3 , 4, 5 ]
> + [ Upa , Upa, Upa, Upa, , ] <logical>s\t%0.b, %1/z, %2.b, %3.b
> + }
> )
Could we leave out these empty trailing constraints? They're quite
common in SVE & SME patterns and are specifically not meant to influence
instruction selection. E.g. we've done the same thing for *cnot<mode>
(to pick a random example).
Agree with Kyrill's ok otherwise.
Richard
