Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk.
gcc/ChangeLog: * config/i386/sse.md (vcond_mask_<mode><mode>): New expander. gcc/testsuite/ChangeLog: * gcc.target/i386/pr114125.c: New test. --- gcc/config/i386/sse.md | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr114125.c | 10 ++++++++++ 2 files changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr114125.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0f4fbcb2c5d..7cd912eeeb1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4807,6 +4807,26 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" DONE; }) +(define_expand "vcond_mask_<mode><mode>" + [(match_operand:SWI1248_AVX512BW 0 "register_operand") + (match_operand:SWI1248_AVX512BW 1 "register_operand") + (match_operand:SWI1248_AVX512BW 2 "register_operand") + (match_operand:SWI1248_AVX512BW 3 "register_operand")] + "TARGET_AVX512F" +{ + /* (operand[1] & operand[3]) | (operand[2] & ~operand[3]) */ + rtx op1 = gen_reg_rtx (<MODE>mode); + rtx op2 = gen_reg_rtx (<MODE>mode); + rtx op3 = gen_reg_rtx (<MODE>mode); + + emit_insn (gen_and<mode>3 (op1, operands[1], operands[3])); + emit_insn (gen_one_cmpl<mode>2 (op3, operands[3])); + emit_insn (gen_and<mode>3 (op2, operands[2], op3)); + emit_insn (gen_ior<mode>3 (operands[0], op1, op2)); + + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel floating point logical operations diff --git a/gcc/testsuite/gcc.target/i386/pr114125.c b/gcc/testsuite/gcc.target/i386/pr114125.c new file mode 100644 index 00000000000..e63fbffe965 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr114125.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v4 -fdump-tree-forwprop3-raw " } */ + +typedef long vec __attribute__((vector_size(16))); +vec f(vec x){ + vec y = x < 10; + return y & (y == 0); +} + +/* { dg-final { scan-tree-dump-not "_expr" "forwprop3" } } */ -- 2.31.1