This patch cleans up the predicates and constraints that are now
redundant after the removal of FPA and Maverick co-processor support.
Tested on arm-eabi.
* arm.md (addsf3, adddf3): Use s_register_operand.
(subsf3, subdf3): Likewise.
(mulsf3, muldf3): Likewise.
(difsf3, divdf3): Likewise.
(movsfcc, movdfcc): Likewise.
* predicates.md (f_register_operand): Delete.
(arm_float_rhs_operand): Delete.
(arm_float_add_operand): Delete.
(arm_float_compare_operand): Use s_register_operand when
there's no VFP.
(cirrus_register_operand): Delete.
(cirrus_fp_register): Delete.
(cirrus_shift_const): Delete.
(cmpdi_operand): Remove Maverick support.
* constraints.md (f, v, H): Delete constraints.
(G): Update documentation.
* arm.c (fp_consts_inited): Convert to bool.
(strings_fp): Delete.
(values_fp): Delete.
(value_fp0): New variable.
(init_fp_table): Simplify logic.
(arm_const_double_rtx): Likewise.
(fp_immediate_constant): Likewise.
(fp_const_from_val): Likewise.
(neg_const_double_rtx_ok_for_fpa): Delete.
* doc/md.texi (ARM constraints): Update documentation.
R.Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 188621)
+++ doc/md.texi (working copy)
@@ -1653,21 +1653,13 @@ table heading for each architecture is t
the meanings of that architecture's constraints.
@table @emph
-@item ARM family---@file{config/arm/arm.h}
+@item ARM family---@file{config/arm/constraints.md}
@table @code
-@item f
-Floating-point register
-
@item w
VFP floating-point register
-@item F
-One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
-or 10.0
-
@item G
-Floating-point constant that would satisfy the constraint @samp{F} if it
-were negated
+The floating-point constant 0.0
@item I
Integer that is valid as an immediate operand in a data processing
Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c (revision 188622)
+++ config/arm/arm.c (working copy)
@@ -8676,33 +8676,18 @@ arm_cortex_a5_branch_cost (bool speed_p,
return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
}
-static int fp_consts_inited = 0;
+static bool fp_consts_inited = false;
-/* Only zero is valid for VFP. Other values are also valid for FPA. */
-static const char * const strings_fp[8] =
-{
- "0", "1", "2", "3",
- "4", "5", "0.5", "10"
-};
-
-static REAL_VALUE_TYPE values_fp[8];
+static REAL_VALUE_TYPE value_fp0;
static void
init_fp_table (void)
{
- int i;
REAL_VALUE_TYPE r;
- if (TARGET_VFP)
- fp_consts_inited = 1;
- else
- fp_consts_inited = 8;
-
- for (i = 0; i < fp_consts_inited; i++)
- {
- r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
- values_fp[i] = r;
- }
+ r = REAL_VALUE_ATOF ("0", DFmode);
+ value_fp0 = r;
+ fp_consts_inited = true;
}
/* Return TRUE if rtx X is a valid immediate FP constant. */
@@ -8719,36 +8704,12 @@ arm_const_double_rtx (rtx x)
if (REAL_VALUE_MINUS_ZERO (r))
return 0;
- for (i = 0; i < fp_consts_inited; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return 1;
-
- return 0;
-}
-
-/* Return TRUE if rtx X is a valid immediate FPA constant. */
-int
-neg_const_double_rtx_ok_for_fpa (rtx x)
-{
- REAL_VALUE_TYPE r;
- int i;
-
- if (!fp_consts_inited)
- init_fp_table ();
-
- REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- r = real_value_negate (&r);
- if (REAL_VALUE_MINUS_ZERO (r))
- return 0;
-
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return 1;
+ if (REAL_VALUES_EQUAL (r, value_fp0))
+ return 1;
return 0;
}
-
/* VFPv3 has a fairly wide range of representable immediates, formed from
"quarter-precision" floating-point values. These can be evaluated using this
formula (with ^ for exponentiation):
@@ -13715,11 +13676,9 @@ fp_immediate_constant (rtx x)
init_fp_table ();
REAL_VALUE_FROM_CONST_DOUBLE (r, x);
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (r, values_fp[i]))
- return strings_fp[i];
- gcc_unreachable ();
+ gcc_assert (REAL_VALUES_EQUAL (r, value_fp0));
+ return "0";
}
/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
@@ -13731,11 +13690,8 @@ fp_const_from_val (REAL_VALUE_TYPE *r)
if (!fp_consts_inited)
init_fp_table ();
- for (i = 0; i < 8; i++)
- if (REAL_VALUES_EQUAL (*r, values_fp[i]))
- return strings_fp[i];
-
- gcc_unreachable ();
+ gcc_assert (REAL_VALUES_EQUAL (*r, value_fp0));
+ return "0";
}
/* Output the operands of a LDM/STM instruction to STREAM.
Index: config/arm/constraints.md
===================================================================
--- config/arm/constraints.md (revision 188621)
+++ config/arm/constraints.md (working copy)
@@ -19,14 +19,16 @@
;; <http://www.gnu.org/licenses/>.
;; The following register constraints have been used:
-;; - in ARM/Thumb-2 state: f, t, v, w, x, y, z
+;; - in ARM/Thumb-2 state: t, w, x, y, z
;; - in Thumb state: h, b
;; - in both states: l, c, k
;; In ARM state, 'l' is an alias for 'r'
+;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
;; The following normal constraints have been used:
-;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
+;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
;; in Thumb-1 state: I, J, K, L, M, N, O
+;; 'H' was previously used for FPA.
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
@@ -39,15 +41,9 @@
;; in Thumb state: Uu, Uw
-(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS"
- "Legacy FPA registers @code{f0}-@code{f7}.")
-
(define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
"The VFP registers @code{s0}-@code{s31}.")
-(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS"
- "The Cirrus Maverick co-processor registers.")
-
(define_register_constraint "w"
"TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
"The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
@@ -213,15 +209,10 @@ (define_constraint "Py"
(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
(define_constraint "G"
- "In ARM/Thumb-2 state a valid FPA immediate constant."
+ "In ARM/Thumb-2 state the floating-point constant 0."
(and (match_code "const_double")
(match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
-(define_constraint "H"
- "In ARM/Thumb-2 state a valid FPA immediate constant when negated."
- (and (match_code "const_double")
- (match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
-
(define_constraint "Dz"
"@internal
In ARM/Thumb-2 state a vector of constant zeros."
Index: config/arm/predicates.md
===================================================================
--- config/arm/predicates.md (revision 188621)
+++ config/arm/predicates.md (working copy)
@@ -60,19 +60,6 @@ (define_predicate "arm_general_register_
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
})
-(define_predicate "f_register_operand"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- /* We don't consider registers whose class is NO_REGS
- to be a register operand. */
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
-})
-
(define_predicate "vfp_register_operand"
(match_code "reg,subreg")
{
@@ -189,18 +176,6 @@ (define_predicate "arm_reload_memory_ope
|| (GET_CODE (op) == REG
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
-;; True for valid operands for the rhs of an floating point insns.
-;; Allows regs or certain consts on FPA, just regs for everything else.
-(define_predicate "arm_float_rhs_operand"
- (ior (match_operand 0 "s_register_operand")
- (and (match_code "const_double")
- (match_test "TARGET_FPA && arm_const_double_rtx (op)"))))
-
-(define_predicate "arm_float_add_operand"
- (ior (match_operand 0 "arm_float_rhs_operand")
- (and (match_code "const_double")
- (match_test "TARGET_FPA && neg_const_double_rtx_ok_for_fpa (op)"))))
-
(define_predicate "vfp_compare_operand"
(ior (match_operand 0 "s_register_operand")
(and (match_code "const_double")
@@ -209,7 +184,7 @@ (define_predicate "vfp_compare_operand"
(define_predicate "arm_float_compare_operand"
(if_then_else (match_test "TARGET_VFP")
(match_operand 0 "vfp_compare_operand")
- (match_operand 0 "arm_float_rhs_operand")))
+ (match_operand 0 "s_register_operand")))
;; True for valid index operands.
(define_predicate "index_operand"
@@ -464,36 +439,8 @@ (define_predicate "thumb_cbrch_target_op
;;-------------------------------------------------------------------------
;;
-;; MAVERICK predicates
-;;
-
-(define_predicate "cirrus_register_operand"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
- || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
-})
-
-(define_predicate "cirrus_fp_register"
- (match_code "reg,subreg")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- return (GET_CODE (op) == REG
- && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
-})
-
-(define_predicate "cirrus_shift_const"
- (and (match_code "const_int")
- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64")))
-
;; iWMMXt predicates
+;;
(define_predicate "imm_or_reg_operand"
(ior (match_operand 0 "immediate_operand")
@@ -563,11 +510,8 @@ (define_predicate "neon_lane_number"
;; Predicates for named expanders that overlap multiple ISAs.
(define_predicate "cmpdi_operand"
- (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
- (and (match_test "TARGET_ARM")
- (match_operand 0 "cirrus_fp_register"))
- (and (match_test "TARGET_32BIT")
- (match_operand 0 "arm_di_operand"))))
+ (and (match_test "TARGET_32BIT")
+ (match_operand 0 "arm_di_operand")))
;; True if the operand is memory reference suitable for a ldrex/strex.
(define_predicate "arm_sync_memory_operand"
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md (revision 188622)
+++ config/arm/arm.md (working copy)
@@ -1060,7 +1060,7 @@ (define_split
(define_expand "addsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(plus:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_add_operand" "")))]
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
@@ -1068,7 +1068,7 @@ (define_expand "addsf3"
(define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_add_operand" "")))]
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1291,16 +1291,16 @@ (define_insn "*arm_decscc"
(define_expand "subsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
- (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (minus:SF (match_operand:SF 1 "s_register_operand" "")
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
(define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
- (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (minus:DF (match_operand:DF 1 "s_register_operand" "")
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1898,7 +1898,7 @@ (define_insn "*maddhidi4tt"
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(mult:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
")
@@ -1906,7 +1906,7 @@ (define_expand "mulsf3"
(define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
"
")
@@ -1915,15 +1915,15 @@ (define_expand "muldf3"
(define_expand "divsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
- (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "")
- (match_operand:SF 2 "arm_float_rhs_operand" "")))]
+ (div:SF (match_operand:SF 1 "s_register_operand" "")
+ (match_operand:SF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"")
(define_expand "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
- (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
- (match_operand:DF 2 "arm_float_rhs_operand" "")))]
+ (div:DF (match_operand:DF 1 "s_register_operand" "")
+ (match_operand:DF 2 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"")
@@ -8037,7 +8037,7 @@ (define_expand "movsfcc"
[(set (match_operand:SF 0 "s_register_operand" "")
(if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
(match_operand:SF 2 "s_register_operand" "")
- (match_operand:SF 3 "arm_float_add_operand" "")))]
+ (match_operand:SF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT"
"
{
@@ -8059,7 +8059,7 @@ (define_expand "movdfcc"
[(set (match_operand:DF 0 "s_register_operand" "")
(if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
- (match_operand:DF 3 "arm_float_add_operand" "")))]
+ (match_operand:DF 3 "s_register_operand" "")))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"
{
