Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan.
https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c Pan -----Original Message----- From: Jeff Law <jeffreya...@gmail.com> Sent: Monday, June 10, 2024 9:50 PM To: Robin Dapp <rdapp....@gmail.com>; Demin Han <demin....@starfivetech.com>; 钟居哲 <juzhe.zh...@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: kito.cheng <kito.ch...@gmail.com>; Li, Pan2 <pan2...@intel.com> Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern On 6/10/24 1:33 AM, Robin Dapp wrote: >> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0? >> >> target = (a == b) ? x : y >> target = (a != b) ? y : x >> >> Are equivalent, even for IEEE IIRC. > > Yes, that should be fine. My concern was not that we do a > canonicalization but that we might not do it for some of the > vector cases. In particular when one of the operands is wrapped > in a vec_duplicate and we end up with it first rather than > second. > > My general feeling is that the patch is good but I wasn't entirely > sure about all cases (in particular in case we transform something > after expand). That's why I would have liked to see at least some > small test cases for it along with the patch (for the combinations > we don't test yet). Ah, OK. Demin, can you some additional test coverage, guided by Robin's concerns above? Thanks, jeff
