Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

[Jeff Law]

On 12/19/23 2:53 AM, Sergei Lewis wrote:
gcc/ChangeLog

     * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New 
function
     declaration.

     * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New
     function: this generates an inline vectorised memory set, if and only if we
     know the entire operation can be performed in a single vector store

     * config/riscv/riscv.md (setmem<mode>): Try riscv_vector::expand_vec_setmem
     for constant lengths

gcc/testsuite/ChangeLog
     * gcc.target/riscv/rvv/base/setmem-1.c: New tests
     * gcc.target/riscv/rvv/base/setmem-2.c: New tests
     * gcc.target/riscv/rvv/base/setmem-3.c: New tests
So I've updated this patch to work on the trunk and run it through 
pre-commit CI.  Results are clean and I've pushed this to the trunk.

Thanks for your patience.

jeff