On 2024-06-22 00:16 Patrick O'Neill <patr...@rivosinc.com> wrote:
>
>Hi Feng,
>
>Pre-commit has flagged a build-failure for patch 2/3:
>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181962244
>
>When applied to 9a76db24e04 i386: Allow all register_operand SUBREGs in
>x86_ternlog_idx.
>
>Re-confirmed locally with 5320bcbd342 xstormy16: Fix
>xs_hi_nonmemory_operand.
>
>Additionally there is an apply failure for patch 3/3.
>
Sorry for the late reply. This is the reason why build failure failed, the
patch 2/3 depends on patch 3/3. Do you know the reason
"Failed to merge in the changes."? Do I need rebase the patch 3/3? Thanks.
>Results can be seen here:
>Series:
>https://patchwork.sourceware.org/project/gcc/list/?series=35407
>Patch 2/3:
>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-2-wangf...@eswincomputing.com/
>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181863112
>Patch 3/3:
>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-3-wangf...@eswincomputing.com/
>https://github.com/ewlu/gcc-precommit-ci/issues/1784#issuecomment-2181861381
>
>Thanks,
>Patrick
>
>On 6/20/24 18:54, Feng Wang wrote:
>> Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
>> functions are added by this patch.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
>> Add 'Zvfbfmin' intrinsic in bases.
>> (class vfwcvtbf16_f): Ditto.
>> (class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases.
>> (BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins-bases.h: Add declaration for 'Zvfbfmin'
>> and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
>> Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'.
>> (vfncvtbf16_f): Ditto.
>> (vfncvtbf16_f_frm): Ditto.
>> (vfwcvtbf16_f): Ditto.
>> (vfwmaccbf16): Ditto.
>> (vfwmaccbf16_frm): Ditto.
>> * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p):
>> Add vector intrinsic build judgment for BFloat16.
>> (build_all): Ditto.
>> (BASE_NAME_MAX_LEN): Adjust max length.
>> * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS):
>> Add new operand type for BFloat16.
>> (vfloat32mf2_t): Ditto.
>> (vfloat32m1_t): Ditto.
>> (vfloat32m2_t): Ditto.
>> (vfloat32m4_t): Ditto.
>> (vfloat32m8_t): Ditto.
>> * config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto.
>> (validate_instance_type_required_extensions):
>> Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins.h (enum required_ext):
>> Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'.
>> (reqired_ext_to_isa_name): Ditto.
>> (required_extensions_specified): Ditto.
>> (struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv.cc (riscv_validate_vector_type):
>> Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>>
>> ---
