> -----Original Message----- > From: Kyrylo Tkachov <ktkac...@nvidia.com> > Sent: Thursday, June 27, 2024 3:49 PM > To: Tamar Christina <tamar.christ...@arm.com> > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw <richard.earns...@arm.com>; > Richard Sandiford <richard.sandif...@arm.com> > Subject: Re: [PATCH] aarch64: Remove RNG and MTE from -mcpu=neoverse-v2 > > Hi Tamar, > Thanks for going through the docs here, > > > On 27 Jun 2024, at 16:19, Tamar Christina <tamar.christ...@arm.com> wrote: > > > > External email: Use caution opening links or attachments > > > > > > Hi Kyrill, > > > >> -----Original Message----- > >> From: Kyrylo Tkachov <ktkac...@nvidia.com> > >> Sent: Thursday, June 27, 2024 9:58 AM > >> To: gcc-patches@gcc.gnu.org > >> Cc: Richard Earnshaw <richard.earns...@arm.com>; Richard Sandiford > >> <richard.sandif...@arm.com> > >> Subject: [PATCH] aarch64: Remove RNG and MTE from -mcpu=neoverse-v2 > >> > >> Hi all, > >> > >> According to the TRM for Neoverse V2 the Memory Tagging and RNG features > >> are optional configurations of the core and may not always be present. > >> Therefore -mcpu=neoverse-v2 shouldn't enable them, similar to how the > >> crypto > >> extensions aren’t enabled by default. > > > > RNG is indeed optional, however Memory Tagging is not. The table is a bit > > cryptic > > but it distinguishes between three states: "supported", "supported using > configurable > > option" and "unsupported". > > > > RNG is supported with configurable option, but MTE is "supported" (this > wording seems to > > be used for things that are mandatory.). If you look in table 2-7 of the > > TRM it > states > > "The Neoverse-V2 core always implements MTE". > > > > This can be confirmed by looking at the table A-204: ID_AA64PFR1_EL1 bit > descriptions. > > For MTE the register cannot be 0b000, i.e. even though MTE is > > architecturally > optional, > > it's not valid for a Neoverse-V2 core not to have MTE. > > > > This means that the compiler should declare support for MTE as at the CPU > > level > it's always > > supported. > > Okay, I guess this is indeed venturing into the grey area of what the > compiler can > enable/use. > My reading of the situation is that the Neoverse V2 core indeed always > supports > MTE instructions like you properly point out. > > However for MTE to actually have any use, the SoC/system needs to implement > the tag storage in the memory system, and not all systems choose to do so. In > that > case the MTE functionality isn’t actually exposed to the user through the OS > (through HWCAPS, /proc/cpuinfo) so it may as well not be present. Perhaps it’s > not useful for users to expose the __ARM_FEATURE_MEMORY_TAGGING macro > and the arm_acle.h intrinsics for it in that case.
Yes, but uses of MTE should normally check for the HWCAPS anyway, as MTE support as you say is configurable. However it's still not the compiler's job. The user should be able to use the intrinsics Because otherwise even if they check HWCAPS they wouldn't be able to use it if they are on an implementation of Neoverse-V2 that has both the system and CPU components implemented. So I believe it's wrong to remove MTE from the compiler flags, as the compiler should be concerned with code generation. And Neoverse-V2 will not fault on MTE instructions. Regards, Tamar > > I’m okay with leaving out the MTE disabling from this patch and just removing > the > RNG option for now. > Thanks, > Kyrill > > > > > Kind Regards, > > Tamar > > > >> > >> Bootstrapped and tested on aarch64-none-linux-gnu. > >> Does this reasoning make sense? > >> Thanks, > >> Kyrill > >
