LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 2
From: Pan Li <pan2...@intel.com>
This patch would like to add test cases for the unsigned scalar
.SAT_ADD IMM form 2. Aka:
Form 2:
#define DEF_SAT_U_ADD_IMM_FMT_2(T) \
T __attribute__((noinline)) \
sat_u_add_imm_##T##_fmt_1 (T x) \
{ \
return (T)(x + 9) < x ? -1 : (x + 9); \
}
DEF_SAT_U_ADD_IMM_FMT_2(uint64_t)
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper test macro.
* gcc.target/riscv/sat_u_add_imm-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-8.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-5.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-6.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-7.c: New test.
* gcc.target/riscv/sat_u_add_imm-run-8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++
.../gcc.target/riscv/sat_u_add_imm-5.c | 19 ++++++++
.../gcc.target/riscv/sat_u_add_imm-6.c | 21 +++++++++
.../gcc.target/riscv/sat_u_add_imm-7.c | 18 ++++++++
.../gcc.target/riscv/sat_u_add_imm-8.c | 17 +++++++
.../gcc.target/riscv/sat_u_add_imm-run-5.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-6.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-7.c | 46 +++++++++++++++++++
.../gcc.target/riscv/sat_u_add_imm-run-8.c | 46 +++++++++++++++++++
9 files changed, 269 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4ec4ec36cc1..d94f0fd602c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -67,9 +67,19 @@ sat_u_add_imm##IMM##_##T##_fmt_1 (T x) \
return (T)(x + IMM) >= x ? (x + IMM) : -1; \
}
+#define DEF_SAT_U_ADD_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline)) \
+sat_u_add_imm##IMM##_##T##_fmt_2 (T x) \
+{ \
+ return (T)(x + IMM) < x ? -1 : (x + IMM); \
+}
+
#define RUN_SAT_U_ADD_IMM_FMT_1(T, x, IMM, expect) \
if (sat_u_add_imm##IMM##_##T##_fmt_1(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_ADD_IMM_FMT_2(T, x, IMM, expect) \
+ if (sat_u_add_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed) */
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
new file mode 100644
index 00000000000..19b502db6c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm9_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*9
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
new file mode 100644
index 00000000000..0317370b67e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-6.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm3_uint16_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*3
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
new file mode 100644
index 00000000000..044b821f7b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-7.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm7_uint32_t_fmt_2:
+** addiw\s+[atx][0-9]+,\s*a0,\s*7
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
new file mode 100644
index 00000000000..4eafb83c756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_imm8_uint64_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*8
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
new file mode 100644
index 00000000000..8e8759c9825
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-5.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 254)
+DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 255)
+
+#define T uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 254, 254, },
+ { 1, 254, 255, },
+ { 2, 254, 255, },
+ { 0, 255, 255, },
+ { 1, 255, 255, },
+ { 2, 255, 255, },
+ { 255, 255, 255, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 254, d[3][2]);
+ RUN (T, d[4][0], 254, d[4][2]);
+ RUN (T, d[5][0], 254, d[5][2]);
+
+ RUN (T, d[6][0], 255, d[6][2]);
+ RUN (T, d[7][0], 255, d[7][2]);
+ RUN (T, d[8][0], 255, d[8][2]);
+ RUN (T, d[9][0], 255, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
new file mode 100644
index 00000000000..7b6bd731234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-6.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65534)
+DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 65535)
+
+#define T uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 65534, 65534, },
+ { 1, 65534, 65535, },
+ { 2, 65534, 65535, },
+ { 0, 65535, 65535, },
+ { 1, 65535, 65535, },
+ { 2, 65535, 65535, },
+ { 65535, 65535, 65535, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 65534, d[3][2]);
+ RUN (T, d[4][0], 65534, d[4][2]);
+ RUN (T, d[5][0], 65534, d[5][2]);
+
+ RUN (T, d[6][0], 65535, d[6][2]);
+ RUN (T, d[7][0], 65535, d[7][2]);
+ RUN (T, d[8][0], 65535, d[8][2]);
+ RUN (T, d[9][0], 65535, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
new file mode 100644
index 00000000000..80241527ee9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-7.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967294)
+DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 4294967295)
+
+#define T uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 4294967294, 4294967294, },
+ { 1, 4294967294, 4294967295, },
+ { 2, 4294967294, 4294967295, },
+ { 0, 4294967295, 4294967295, },
+ { 1, 4294967295, 4294967295, },
+ { 2, 4294967295, 4294967295, },
+ { 4294967295, 4294967295, 4294967295, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 4294967294, d[3][2]);
+ RUN (T, d[4][0], 4294967294, d[4][2]);
+ RUN (T, d[5][0], 4294967294, d[5][2]);
+
+ RUN (T, d[6][0], 4294967295, d[6][2]);
+ RUN (T, d[7][0], 4294967295, d[7][2]);
+ RUN (T, d[8][0], 4294967295, d[8][2]);
+ RUN (T, d[9][0], 4294967295, d[9][2]);
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
new file mode 100644
index 00000000000..4a76dbb6dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm-run-8.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 1)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551614u)
+DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 18446744073709551615u)
+
+#define T uint64_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_ADD_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 1, },
+ { 1, 1, 2, },
+ { 0, 18446744073709551614u, 18446744073709551614u, },
+ { 1, 18446744073709551614u, 18446744073709551615u, },
+ { 2, 18446744073709551614u, 18446744073709551615u, },
+ { 0, 18446744073709551615u, 18446744073709551615u, },
+ { 1, 18446744073709551615u, 18446744073709551615u, },
+ { 2, 18446744073709551615u, 18446744073709551615u, },
+ { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, },
+};
+
+int
+main ()
+{
+ RUN (T, d[0][0], 0, d[0][2]);
+
+ RUN (T, d[1][0], 1, d[1][2]);
+ RUN (T, d[2][0], 1, d[2][2]);
+
+ RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+ RUN (T, d[4][0], 18446744073709551614u, d[4][2]);
+ RUN (T, d[5][0], 18446744073709551614u, d[5][2]);
+
+ RUN (T, d[6][0], 18446744073709551615u, d[6][2]);
+ RUN (T, d[7][0], 18446744073709551615u, d[7][2]);
+ RUN (T, d[8][0], 18446744073709551615u, d[8][2]);
+ RUN (T, d[9][0], 18446744073709551615u, d[9][2]);
+
+ return 0;
+}
--
2.34.1
