On 7/24/24 12:06 PM, Segher Boessenkool wrote: > On Tue, Jul 23, 2024 at 04:26:43PM -0500, Peter Bergner wrote: >> On 7/19/24 3:04 PM, Carl Love wrote: >>> (define_insn "vs<SLDB_lr>db_<mode>" >>> - [(set (match_operand:VI2 0 "register_operand" "=v") >>> - (unspec:VI2 [(match_operand:VI2 1 "register_operand" "v") >>> - (match_operand:VI2 2 "register_operand" "v") >>> + [(set (match_operand:VEC_IC 0 "register_operand" "=v") >>> + (unspec:VEC_IC [(match_operand:VEC_IC 1 "register_operand" "v") >>> + (match_operand:VEC_IC 2 "register_operand" "v") >>> (match_operand:QI 3 "const_0_to_12_operand" "n")] >>> VSHIFT_DBL_LR))] >>> "TARGET_POWER10" >> >> I know the old code used the register_operand predicate for the vector >> operands, but those really should be changed to altivec_register_operand. > > register_operand is just fine usually. The "v" constraint already makes > sure things end up in a VMX (a lower VSX) register, the predicate > doesn't help here. register_operand is shorter (and thus, preferred), > and also more likely correct if the code changes later :-)
I thought we always wanted the predicate to match the constraint being used? Peter
