> -----Original Message----- > From: Jakub Jelinek <ja...@redhat.com> > Sent: Friday, July 26, 2024 7:59 PM > To: Jiang, Haochen <haochen.ji...@intel.com> > Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao <hongtao....@intel.com>; > ubiz...@gmail.com > Subject: Re: [PATCH v2] i386: Fix AVX512 intrin macro typo > > On Fri, Jul 26, 2024 at 04:10:48PM +0800, Haochen Jiang wrote: > > * config/i386/avx512dqintrin.h > > (_mm_mask_fpclass_ss_mask): Correct operand order. > > (_mm_mask_fpclass_sd_mask): Ditto. > > (_mm_reduce_round_sd): Use -1 as mask since it is non-mask. > > (_mm_reduce_round_ss): Ditto. > > You haven't mentioned the > (_mm_maskz_reduce_round_ss): Use > __builtin_ia32_reducess_mask_round > instead of __builtin_ia32_reducesd_mask_round. > change here. > > > * config/i386/avx512vlbwintrin.h > > (_mm256_mask_alignr_epi8): Correct operand usage. > > (_mm_mask_alignr_epi8): Ditto. > > * config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/i386/avx512bw-vpalignr-1b.c: New test. > > * gcc.target/i386/avx512dq-vfpclasssd-1b.c: Ditto. > > * gcc.target/i386/avx512dq-vfpclassss-1b.c: Ditto. > > * gcc.target/i386/avx512dq-vreducesd-1b.c: Ditto. > > * gcc.target/i386/avx512dq-vreducess-1b.c: Ditto. > > * gcc.target/i386/avx512vl-valignq-1b.c: Ditto. > > I went through all the cases and agree with all the changes. > > LGTM with the above ChangeLog nit fixed, for trunk/release branches, even for > 14.2 if committed RSN.
Ok. I will commit them and backport them to GCC13 and GCC12 now. For GCC14, we could wait for GCC14.3 since it has been a weekend passed and not that RSN. But if it could be in GCC14.2, I will also happy for that. Thx, Haochen > > Jakub
