On 7/30/24 7:01 AM, Lulu Cheng wrote:
在 2024/7/26 下午8:43, Xi Ruoyao 写道:
We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions. But this
does not always work: for cases like x << 1 | y, the compiler
tends to do
(sign_extend:DI
(ior:SI (ashift:SI (reg:SI $r4)
(const_int 1))
(reg:SI $r5)))
instead of
(ior:DI (sign_extend:DI (ashift:SI (reg:SI $r4) (const_int 1)))
(sign_extend:DI (reg:SI $r5)))
So we cannot match the ashlsi3_extend instruction here and we get:
slli.w $r4,$r4,1
or $r4,$r5,$r4
slli.w $r4,$r4,0 # <= redundant
jr $r1
To eliminate this redundant extension we need to turn SImode shift etc.
to DImode "si3_extend" operations earlier, when we expand the SImode
operation. We are already doing this for addition, now do it for
shifts, rotates, substract, multiplication, division, and modulo as
well.
The bytepick.w definition for TARGET_64BIT needs to be adjusted so it
won't be undone by the shift expanding.
LGTM!
I don't know if there will be redundant symbol extension directives
after this change.:-(
We've had very good success with this approach on RISC-V. It's not
perfect and may highlight the need for a few additional patterns, but
overall it was very much a step in the right direction.
Jeff
