On 8/29/24 10:13 AM, John David Anglin wrote:
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11.
Committed to trunk.
Dave
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hppa: Fix handling of unscaled index addresses on HP-UX
The PA-RISC architecture uses the top two bits of memory pointers
to select space registers. The space register ID is ored with the
pointer offset to compute the global virtual address for an access.
The new late combine passes broke gcc on HP-UX. One of these passes
runs after reload. The existing code assumed no unscaled index
instructions would be created after reload as the REG_POINTER flag
is not reliable after reload. The new pass sometimes interchanged
the base and index registers, causing these instructions to fault
when the wrong space register was selected.
Implicit space register selection based on the index rather than the
effective address. A thorn in my side for years working on the PA.
The flag is not propagated when a constant is added to a pointer.
IIRC one of the problems in this space was Ada would tend to create
pointers outside an object's bounds, then use an offset to bring the
effective address back into the object. And tail merging would tend to
do things like see a path with a + b and another with b + a as addresses
and assume it could commonize the paths. All kinds of dragons in here.
I tried damn hard to support unscaled indexing, but it was always quite
painful.
Thus, I came to the conclusion that the best approach was to
disable use of unscaled index addresses on HP-UX. I don't think
this impacts performance significantly. Code size might get
slightly larger but we get some or more back from having the late
combine passes.
I can certainly live with this as I don't have to use HPUX anymore ;-)
Presumably Linux has a flat address model with the space registers
holding the same value. That's what we did with our BSD and Mach ports
to the PA and was what PRO was recommending to members back in the day...
It may be worth noting that if anyone still has mn10300 silicon it had
similar properties. Though it may have been limited to the first
generation, I vaguely recall a Matsushita engineer I worked with
indicating they considered it a silicon bug.
jeff
