Re: [PATCH v2 8/8] RISC-V: Add else operand to masked loads [PR115336].

[Jeff Law]

On 10/18/24 8:22 AM, Robin Dapp wrote:

This patch adds else operands to masked loads.  Currently the default
else operand predicate accepts "undefined" (i.e. SCRATCH) as well as
all-ones values.

Note that this series introduces a large number of new RVV FAILs for
riscv.  All of them are due to us not being able to elide redundant
vec_cond_exprs.

        PR middle-end/115336
        PR middle-end/116059

gcc/ChangeLog:

        * config/riscv/autovec.md: Add else operand.
        * config/riscv/predicates.md (maskload_else_operand): New
        predicate.
        * config/riscv/riscv-v.cc (get_else_operand): Remove static.
        (expand_load_store): Use get_else_operand and adjust index.
        (expand_gather_scatter): Ditto.
        (expand_lanes_load_store): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/pr115336.c: New test.
        * gcc.target/riscv/rvv/autovec/pr116059.c: New test.

OK once prereqs are resolved.

jeff