[gcc-wwwdocs PATCH] gcc-15: Mention new ISA and Diamond Rapids support for x86_64 backend

[Haochen Jiang]

Hi all,

This patch will add recent new ISA and arch support for x86_64 backend into
gcc-wwwdocs.

Ok for gcc-wwwdocs?

Thx,
Haochen

---
 htdocs/gcc-15/changes.html | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 46dad391..d138942c 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -191,12 +191,49 @@ a work-in-progress.</p>
 <h3 id="x86">IA-32/x86-64</h3>
 
 <ul>
+  <li>New ISA extension support for Intel AMX-AVX512 was added.
+      AMX-AVX512 intrinsics are available via the <code>-mamx-avx512</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AMX-FP8 was added.
+      AMX-FP8 intrinsics are available via the <code>-mamx-fp8</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AMX-MOVRS was added.
+      AMX-MOVRS intrinsics are available via the <code>-mamx-movrs</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AMX-TF32 was added.
+      AMX-TF32 intrinsics are available via the <code>-mamx-tf32</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AMX-TRANSPOSE was added.
+      AMX-TRANSPOSE intrinsics are available via the 
<code>-mamx-transpose</code>
+      compiler switch.
+  </li>
   <li>New ISA extension support for Intel AVX10.2 was added.
       AVX10.2 intrinsics are available via the <code>-mavx10.2</code> or
       <code>-mavx10.2-256</code> compiler switch with 256-bit vector size
       support. 512-bit vector size support for AVX10.2 intrinsics are
       available via the <code>-mavx10.2-512</code> compiler switch.
   </li>
+  <li>New ISA extension support for Intel MOVRS was added.
+      MOVRS intrinsics are available via the <code>-mmovrs</code>
+      compiler switch. 128 and 256 bit MOVRS intrinsics are available via the
+      <code>-mmovrs -mavx10.2</code> compiler switch. 512 bit MOVRS intrinsics
+      are available via the <code>-mmovrs -mavx10.2-512</code> compiler switch.
+  </li>
+  <li>The EVEX version support for Intel SM4 was added.
+      New 512-bit SM4 intrinsics are available via the
+      <code>-msm4 -mavx10.2-512</code> compiler switch.
+  </li>
+  <li>GCC now supports the Intel CPU named Diamond Rapids through
+    <code>-march=diamondrapids</code>.
+    Based on Granite Rapids, the switch further enables the AMX-AVX512,
+    AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2 with 512 bit
+    support, AVX-IFMA. AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8,
+    CMPccXADD, MOVRS, SHA512, SM3, SM4 and USER_MSR ISA extensions.
+  </li>
   <li>Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were
       removed in GCC 15. GCC will no longer accept <code>-march=knl</code>,
       <code>-march=knm</code>,<code>-mavx5124fmaps</code>,
-- 
2.31.1