Since XTheadvector does not support vsetivli, vl needs to be put into
registers during the expand phase.
PR 116593
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::add_input_operand):
Put const to GPR for vl
* config/riscv/thead-vector.md (@th_pred_vl_mov<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr116593.c: New test.
Reported-by: nihui <[email protected]>
---
gcc/config/riscv/riscv-vector-builtins.cc | 18 +++++++++++++++++-
gcc/config/riscv/thead-vector.md | 13 +++++++++++++
.../riscv/rvv/xtheadvector/pr116593.c | 13 +++++++++++++
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116593.c
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 458d9b0886e3..cf2344e54c21 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3936,7 +3936,23 @@ function_expander::add_input_operand (unsigned argno)
{
tree arg = CALL_EXPR_ARG (exp, argno);
rtx x = expand_normal (arg);
- add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
+
+ /* Since the parameter vl of XTheadVector does not support
+ immediate numbers, we need to put it in the register
+ in advance. */
+ if (TARGET_XTHEADVECTOR
+ && CONST_INT_P (x)
+ && base->apply_vl_p ()
+ && argno == (unsigned) (call_expr_nargs (exp) - 1)
+ && !rtx_equal_p (x, const0_rtx))
+ {
+ rtx tmp = gen_reg_rtx (Pmode);
+ /* Use UNSPEC to avoid being optimized before vsetvl pass. */
+ emit_insn (gen_th_pred_vl_mov (Pmode, tmp, x));
+ add_input_operand (TYPE_MODE (TREE_TYPE (arg)), tmp);
+ }
+ else
+ add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
}
/* Since we may normalize vop/vop_tu/vop_m/vop_tumu.. into a single patter.
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5fe9ba08c4eb..0e00514c6b2d 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -25,6 +25,7 @@ (define_c_enum "unspec" [
UNSPEC_TH_VSUXW
UNSPEC_TH_VWLDST
+ UNSPEC_TH_VL_MOV
])
(define_int_iterator UNSPEC_TH_VLMEM_OP [
@@ -93,6 +94,18 @@ (define_int_iterator UNSPEC_TH_VSXMEM_OP [
(define_mode_iterator V_VLS_VT [V VLS VT])
(define_mode_iterator V_VB_VLS_VT [V VB VLS VT])
+(define_insn_and_split "@th_pred_vl_mov<mode>"
+ [(set (match_operand:P 0 "register_operand" "=r")
+ (unspec:P
+ [(match_operand:P 1 "const_int_operand" " i")]
+ UNSPEC_TH_VL_MOV))]
+ "TARGET_XTHEADVECTOR"
+ "li\t%0,%1"
+ "&& epilogue_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ {}
+ [(set_attr "type" "arith")])
+
(define_split
[(set (match_operand:V_VB_VLS_VT 0 "reg_or_mem_operand")
(match_operand:V_VB_VLS_VT 1 "reg_or_mem_operand"))]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116593.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116593.c
new file mode 100644
index 000000000000..2d5b04207962
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116593.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2 -save-temps"
{ target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2 -save-temps" {
target { rv64 } } } */
+
+#include <riscv_vector.h>
+
+vfloat16m1_t
+foo (vfloat16m1_t x)
+{
+ return __riscv_vfadd_vf_f16m1 (x, 1, 1);
+}
+
+/* { dg-final { scan-assembler-times {th\.vfadd\.vf} 1 } } */
--
2.25.1
