Hi,
When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version. I think it
is an oversight, this patch is to consider veqv as well.
Bootstrapped and regtested on ppc64-linux P8/P9 and
ppc64le-linux P9/P10 two months ago, re-tested (also rebased)
on ppc64le-linux P10 again.
I'm going to push this next week if no objections.
BR,
Kewen
-----
gcc/ChangeLog:
* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.
---
gcc/config/rs6000/rs6000.md | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2598059280b..ca91a24795b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7557,9 +7557,12 @@ (define_insn_and_split "*eqv<mode>3_internal1"
(match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
"TARGET_P8_VECTOR"
{
- if (vsx_register_operand (operands[0], <MODE>mode))
+ if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
return "xxleqv %x0,%x1,%x2";
+ if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
+ return "veqv %0,%1,%2";
+
return "#";
}
"TARGET_P8_VECTOR && reload_completed
--
2.43.5
