On Fri, 6 Dec 2024, Richard Earnshaw wrote:
> The vcond{,u} expander paterns have been declared as obsolete. Remove
> them from the Arm backend.
OK (not sure if you were expecting approval from me ;)), the patterns
are no longer exercised anywhere.
Richard.
> gcc/ChangeLog:
>
> PR target/114189
> * config/arm/arm-protos.h (arm_expand_vcond): Delete prototype.
> * config/arm/arm.cc (arm_expand_vcond): Delete function.
> * config/arm/vec-common.md (vcond<mode><mode>): Delete pattern
> (vcond<V_cvtto><mode>): Likewise.
> (vcond<VH_cvtto><mode>): Likewise.
> (vcondu<mode><v_cmp_result>): Likewise.
> ---
> gcc/config/arm/arm-protos.h | 1 -
> gcc/config/arm/arm.cc | 44 ----------------------
> gcc/config/arm/vec-common.md | 71 ------------------------------------
> 3 files changed, 116 deletions(-)
>
> No regressions in the testsuite. I'll push next week if there are no
> objections.
>
> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
> index 7311ad4d8e4..155507f4745 100644
> --- a/gcc/config/arm/arm-protos.h
> +++ b/gcc/config/arm/arm-protos.h
> @@ -406,7 +406,6 @@ extern bool arm_expand_vector_compare (rtx, rtx_code,
> rtx, rtx, bool);
> #endif /* RTX_CODE */
>
> extern bool arm_gen_setmem (rtx *);
> -extern void arm_expand_vcond (rtx *, machine_mode);
> extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
>
> extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
> diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
> index 1fbc4c22f22..bc6f9345d1e 100644
> --- a/gcc/config/arm/arm.cc
> +++ b/gcc/config/arm/arm.cc
> @@ -31803,50 +31803,6 @@ arm_expand_vector_compare (rtx target, rtx_code
> code, rtx op0, rtx op1,
> }
> }
>
> -/* Expand a vcond or vcondu pattern with operands OPERANDS.
> - CMP_RESULT_MODE is the mode of the comparison result. */
> -
> -void
> -arm_expand_vcond (rtx *operands, machine_mode cmp_result_mode)
> -{
> - /* When expanding for MVE, we do not want to emit a (useless) vpsel in
> - arm_expand_vector_compare, and another one here. */
> - rtx mask;
> -
> - if (TARGET_HAVE_MVE)
> - mask = gen_reg_rtx (arm_mode_to_pred_mode (cmp_result_mode).require ());
> - else
> - mask = gen_reg_rtx (cmp_result_mode);
> -
> - bool inverted = arm_expand_vector_compare (mask, GET_CODE (operands[3]),
> - operands[4], operands[5], true);
> - if (inverted)
> - std::swap (operands[1], operands[2]);
> - if (TARGET_NEON)
> - emit_insn (gen_neon_vbsl (GET_MODE (operands[0]), operands[0],
> - mask, operands[1], operands[2]));
> - else
> - {
> - machine_mode cmp_mode = GET_MODE (operands[0]);
> -
> - switch (GET_MODE_CLASS (cmp_mode))
> - {
> - case MODE_VECTOR_INT:
> - emit_insn (gen_mve_q (VPSELQ_S, VPSELQ_S, cmp_mode, operands[0],
> - operands[1], operands[2], mask));
> - break;
> - case MODE_VECTOR_FLOAT:
> - if (TARGET_HAVE_MVE_FLOAT)
> - emit_insn (gen_mve_q_f (VPSELQ_F, cmp_mode, operands[0],
> - operands[1], operands[2], mask));
> - else
> - gcc_unreachable ();
> - break;
> - default:
> - gcc_unreachable ();
> - }
> - }
> -}
>
> #define MAX_VECT_LEN 16
>
> diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
> index ff1c27a0d71..0b426cdaff7 100644
> --- a/gcc/config/arm/vec-common.md
> +++ b/gcc/config/arm/vec-common.md
> @@ -416,77 +416,6 @@ (define_expand "vlshr<mode>3"
> }
> })
>
> -;; Conditional instructions. These are comparisons with conditional moves
> for
> -;; vectors. They perform the assignment:
> -;;
> -;; Vop0 = (Vop4 <op3> Vop5) ? Vop1 : Vop2;
> -;;
> -;; where op3 is <, <=, ==, !=, >= or >. Operations are performed
> -;; element-wise.
> -
> -(define_expand "vcond<mode><mode>"
> - [(set (match_operand:VDQWH 0 "s_register_operand")
> - (if_then_else:VDQWH
> - (match_operator 3 "comparison_operator"
> - [(match_operand:VDQWH 4 "s_register_operand")
> - (match_operand:VDQWH 5 "reg_or_zero_operand")])
> - (match_operand:VDQWH 1 "s_register_operand")
> - (match_operand:VDQWH 2 "s_register_operand")))]
> - "ARM_HAVE_<MODE>_ARITH
> - && !TARGET_REALLY_IWMMXT
> - && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
> -{
> - arm_expand_vcond (operands, <V_cmp_result>mode);
> - DONE;
> -})
> -
> -(define_expand "vcond<V_cvtto><mode>"
> - [(set (match_operand:<V_CVTTO> 0 "s_register_operand")
> - (if_then_else:<V_CVTTO>
> - (match_operator 3 "comparison_operator"
> - [(match_operand:V32 4 "s_register_operand")
> - (match_operand:V32 5 "reg_or_zero_operand")])
> - (match_operand:<V_CVTTO> 1 "s_register_operand")
> - (match_operand:<V_CVTTO> 2 "s_register_operand")))]
> - "ARM_HAVE_<MODE>_ARITH
> - && !TARGET_REALLY_IWMMXT
> - && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
> -{
> - arm_expand_vcond (operands, <V_cmp_result>mode);
> - DONE;
> -})
> -
> -(define_expand "vcond<VH_cvtto><mode>"
> - [(set (match_operand:<VH_CVTTO> 0 "s_register_operand")
> - (if_then_else:<VH_CVTTO>
> - (match_operator 3 "comparison_operator"
> - [(match_operand:V16 4 "s_register_operand")
> - (match_operand:V16 5 "reg_or_zero_operand")])
> - (match_operand:<VH_CVTTO> 1 "s_register_operand")
> - (match_operand:<VH_CVTTO> 2 "s_register_operand")))]
> - "ARM_HAVE_<MODE>_ARITH
> - && !TARGET_REALLY_IWMMXT
> - && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
> -{
> - arm_expand_vcond (operands, <V_cmp_result>mode);
> - DONE;
> -})
> -
> -(define_expand "vcondu<mode><v_cmp_result>"
> - [(set (match_operand:VDQW 0 "s_register_operand")
> - (if_then_else:VDQW
> - (match_operator 3 "arm_comparison_operator"
> - [(match_operand:<V_cmp_result> 4 "s_register_operand")
> - (match_operand:<V_cmp_result> 5 "reg_or_zero_operand")])
> - (match_operand:VDQW 1 "s_register_operand")
> - (match_operand:VDQW 2 "s_register_operand")))]
> - "ARM_HAVE_<MODE>_ARITH
> - && !TARGET_REALLY_IWMMXT"
> -{
> - arm_expand_vcond (operands, <V_cmp_result>mode);
> - DONE;
> -})
> -
> (define_expand "vec_load_lanesoi<mode>"
> [(set (match_operand:OI 0 "s_register_operand")
> (unspec:OI [(match_operand:OI 1 "neon_struct_operand")
>
--
Richard Biener <[email protected]>
SUSE Software Solutions Germany GmbH,
Frankenstrasse 146, 90461 Nuernberg, Germany;
GF: Ivo Totev, Andrew McDonald, Werner Knoblich; (HRB 36809, AG Nuernberg)
