On Thu, Jul 19, 2012 at 11:03:25AM +0200, Uros Bizjak wrote:
> + /* Set CF to specified value. */
> + emit_insn (gen_addqi3_cc(
> + gen_reg_rtx(QImode),
> + op1,
> + constm1_rtx));
> +
>
> This should be in the *.md expander.
Note also that the formatting of the above was wrong for multiple reasons.
> (define_insn "*prefetch_3dnow_<mode>"
> [(prefetch (match_operand:P 0 "address_operand" "p")
> - (match_operand:SI 1 "const_int_operand" "n")
> + (const_int 0)
> (const_int 3))]
> "TARGET_3DNOW"
> -{
> - if (INTVAL (operands[1]) == 0)
> - return "prefetch\t%a0";
> - else
> - return "prefetchw\t%a0";
> -}
> + "prefetch\t%a0"
>
> You have a mnemonic clash here. prefetchw is not good name for a new
> instruction, it clashes with existing 3dnow name. Intel will need to
> fix the spec, you probably won't be able to change prefetchw encoding
> in binutils.
>From what I understand, Intel is using the same encoding of that insn as
3dNOW!, so there is no clash, just the same insn is now enabled by two ISAs
(3dNOW! and this new CPUID prfchw bit).
Jakub
