Hi,
the zbb-rol-ror and stack_save_restore tests use the -fno-lto option and
scan the final assembly. For an invocation like -flto ... -fno-lto the
output file we scan is still something like
zbb-rol-ror-09.ltrans0.ltrans.s.
Therefore skip the tests when "-flto" is present. This gets rid
of a few UNRESOLVED tests.
Regtested on rv64gcv_zvl512b. Going to push if the CI agrees.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack_save_restore_1.c: Skip for -flto.
* gcc.target/riscv/stack_save_restore_2.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-04.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-05.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-06.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-07.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-08.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-09.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c | 3 ++-
gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c | 3 ++-
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c | 4 ++--
8 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
index d8b0668a820..e0a7c68760a 100644
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops
-fno-lto" } */
+/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
char my_getchar();
diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
index 5f0389243b1..aadeaa58230 100644
--- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
+++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops
-fno-lto" } */
+/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2
-fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
char my_getchar();
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
index 28350e5e937..b413b10ea93 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
index cc44653acfb..179477ed93b 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
index 7a98a5712bf..b5f0b8b9027 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
index a08a9eb772e..037230625fb 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
index bf19b76b431..b3864e72ca6 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
index 5c4b9f58de1..121dca90d12 100644
--- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
-/* { dg-skip-if "" { *-*-* } { "-g" } } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */
/* { dg-final { check-function-bodies "**" "" } } */
/* { dg-final { scan-assembler-not {\mand} } } */
--
2.47.1
