> Since the parameter vl of XTheadVector does not support immediate numbers, we
> need
> to put it in the register in advance. That generates the initial code
> correctly.
>
> PR 116593
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::add_input_operand):
> Put immediate for vl to GPR for XTheadVector.
Generally both patches look reasonable to me and the change is less invasive
than going via spec_restriction.
How was this tested? The Rivos CI has already picked it up but please still
always specify. Thanks.
> + /* Since the parameter vl of XTheadVector does not support
> + immediate numbers, we need to put it in the register
> + in advance. */
> + if (TARGET_XTHEADVECTOR
> + && CONST_INT_P (x)
> + && base->apply_vl_p ()
> + && argno == (unsigned) (call_expr_nargs (exp) - 1)
> + && x != CONST0_RTX (GET_MODE (x)))
> + {
> + x = force_reg (word_mode, x);
> + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
> + }
> + else
> + add_input_operand (TYPE_MODE (TREE_TYPE (arg)), x);
> }
To me it feels as if this would better fit one level higher rather than
checking ARGNO and apply_vl_p here. Is that somehow too cumbersome?
> +# GCC testsuite that uses the `dg.exp' driver.
> +
> +# Test the front-end for C++.
> +# We don't need to test back-end code-gen in RV32 system for C++
> +# Because it is already tested in C.
> +# Exit immediately if this isn't a RISC-V target.
> +if ![istarget riscv*-*-*] then {
> + return
> +}
Might want to adjust those comments slightly ;)
--
Regards
Robin
