[PATCH] aarch64: Add missing simd requirements for INS [PR118531]

[Richard Sandiford]

In g:b096a6ebe9d9f9fed4c105f6555f724eb32af95c I'd forgotten
to gate some uses of INS on TARGET_SIMD.

Tested on aarch64-linux-gnu.  I'll push around this time on Monday
if there are no comments before then.

Richard


gcc/
        PR target/118531
        * config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
        (*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
        (*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
        simd requirements.

gcc/testsuite/
        * gcc.target/aarch64/ins_bitfield_1a.c: New test.
        * gcc.target/aarch64/ins_bitfield_3a.c: Likewise.
        * gcc.target/aarch64/ins_bitfield_5a.c: Likewise.
---
 gcc/config/aarch64/aarch64.md                      | 9 ++++++---
 gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c | 8 ++++++++
 gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c | 8 ++++++++
 gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c | 8 ++++++++
 4 files changed, 30 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 44f5b7a54d2..1b67ccc31dd 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6361,7 +6361,8 @@ (define_insn "*insv_reg<mode>_<SUBDI_BITS>"
       return "ins\t%0.<bits_etype>[%1], %2.<bits_etype>[0]";
     return "ins\t%0.<bits_etype>[%1], %w2";
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 (define_insn "*insv_reg<mode>"
@@ -6394,7 +6395,8 @@ (define_insn_and_split 
"*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>"
     operands[2] = lowpart_subreg (<GPI:MODE>mode, operands[2],
                                  <ALLX:MODE>mode);
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 (define_insn "*aarch64_bfi<GPI:mode><ALLX:mode>4"
@@ -6426,7 +6428,8 @@ (define_insn_and_split 
"*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>"
   {
     operands[2] = lowpart_subreg (DImode, operands[3], <ALLX:MODE>mode);
   }
-  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")]
+  [(set_attr "type" "bfm,neon_ins_q,neon_ins_q")
+   (set_attr "arch" "*,simd,simd")]
 )
 
 ;;  Match a bfi instruction where the shift of OP3 means that we are
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c 
b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c
new file mode 100644
index 00000000000..028d4aa1e89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_1a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_1.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c 
b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c
new file mode 100644
index 00000000000..1c153667a8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_3a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_3.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c 
b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c
new file mode 100644
index 00000000000..f6bdde97f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ins_bitfield_5a.c
@@ -0,0 +1,8 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+#pragma GCC target "+nosimd"
+
+#include "ins_bitfield_5.c"
+
+/* { dg-final { scan-assembler-not {\tins\t} } } */
-- 
2.25.1