This patch support svadu and svade extension.
To enable GCC to recognize and process svadu and svade extension correctly at
compile time.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_ext_version_table) New extension.
(riscv_ext_flag_table) Ditto.
* config/riscv/riscv-opts.h: New mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-45.c: New test.
gcc/doc:
* doc/invoke.texi(RISC-V Options): New extension
Signed-off-by: Mingzhu Yan <[email protected]>
---
gcc/common/config/riscv/riscv-common.cc | 10 +++++++---
gcc/config/riscv/riscv.opt | 4 ++++
gcc/doc/invoke.texi | 8 ++++++++
gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++
gcc/testsuite/gcc.target/riscv/arch-46.c | 5 +++++
5 files changed, 29 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index b34409adf..5117ebb9a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -409,6 +409,8 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
{"sstc", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"svade", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"svadu", ISA_SPEC_CLASS_NONE, 1, 0},
{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
{"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1732,9 +1734,11 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP),
RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT),
- RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
- RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
- RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
+ RISCV_EXT_FLAG_ENTRY ("svade", x_riscv_sv_subext, MASK_SVADE),
+ RISCV_EXT_FLAG_ENTRY ("svadu", x_riscv_sv_subext, MASK_SVADU),
+ RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
+ RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
+ RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7515c8ea1..6e9bf60d7 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -466,6 +466,10 @@ Mask(XCVBI) Var(riscv_xcv_subext)
TargetVariable
int riscv_sv_subext
+Mask(SVADE) Var(riscv_sv_subext)
+
+Mask(SVADU) Var(riscv_sv_subext)
+
Mask(SVINVAL) Var(riscv_sv_subext)
Mask(SVNAPOT) Var(riscv_sv_subext)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1819bcdcd..69152cfe8 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31222,6 +31222,14 @@ to @samp{zvks} and @samp{zvkg}.
@tab 1.0
@tab Supervisor-mode timer interrupts extension.
+@item svade
+@tab 1.0
+@tab Cause exception when hardware updating of A/D bits is disabled
+
+@item svadu
+@tab 1.0
+@tab Hardware Updating of A/D Bits extension.
+
@item svinval
@tab 1.0
@tab Fine-grained address-translation cache invalidation extension.
diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c
b/gcc/testsuite/gcc.target/riscv/arch-45.c
new file mode 100644
index 000000000..afffb9955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-45.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c
b/gcc/testsuite/gcc.target/riscv/arch-46.c
new file mode 100644
index 000000000..2a062172e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-46.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */
+int foo()
+{
+}
--
2.43.0
