+ bool is_misaligned = scalar_align < inner_vectype_sz;
+ bool is_packed = scalar_align > 1 && is_misaligned;
+
+ *misalignment = !is_misaligned ? 0 : inner_vectype_sz -
scalar_align;
+
+ if (targetm.vectorize.support_vector_misalignment
+ (TYPE_MODE (vectype), inner_vectype, *misalignment, is_packed))
the misalignment argument is meaningless, I think you want to
pass DR_MISALIGNMENT_UNKNOWN for this and just pass is_packed
if the scalars acesses are not at least size aligned.
At least aarch64's (and loongarch's) support_vector_misalignment gives up
right away if misalignment == -1 (before checking for !is_packed)
and would thus get dr_unaligned_unsupported in case of strict alignment.
I used the same logic for riscv which made a proper value in *misalignment
necessary.
We only have one other invocation of support_vector_misalignment in
tree-vect-data-refs which only sets packed if DR_MISALIGNMENT_UNKOWN.
So ISTM that
if (!is_packed)
return true;
should always be done before acting on DR_MISALIGNMENT_UNKOWN?
Or can there be instances where is_packed == false && DR_MISALIGNMENT_UNKNOWN
and we don't support the misalignment? Like if the target requires
vector-sized alignment?
So my current plan would be to adjust the riscv hook to always support
misalignment if !is_packed regardless of DR_MISALIGNMENT_UNKNOWN and do the
same for aarch64, loongarch?
I'll also change the hook docs to something like
diff --git a/gcc/target.def b/gcc/target.def
index 38903eb567a..94ccf86233c 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -1926,7 +1926,8 @@ DEFHOOK
store/load of a specific factor denoted in the @var{misalignment}\n\
parameter. The vector store/load should be of machine mode @var{mode} and\n\
the elements in the vectors should be of type @var{type}. @var{is_packed}\n\
-parameter is true if the memory access is defined in a packed struct.",
+parameter is true if the misalignment is unknown and the memory access is\n\
+defined in a packed struct."
Note the hook really doesn't know whether you ask it for gather/scatter
or a contiguous vector load so I wonder whether the above fits
constraints on other platforms where scalar accesses might be
allowed to be packed but all unaligned vector accesses would need
to be element aligned?
We actually can have all four combinations of scalar and vector misalignment
support on riscv :/
--
Regards
Robin
