On Tue, Jul 15, 2025 at 3:43 AM H.J. Lu <hjl.to...@gmail.com> wrote:
>
> For MMX 16-bit, 32-bit and 64-bit constant vector loads from constant
> vector pool:
>
> (insn 6 2 7 2 (set (reg:V1SI 5 di)
> (mem/u/c:V1SI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S4 A32]))
> "pr1
> 21062-2.c":10:3 2036 {*movv1si_internal}
> (expr_list:REG_EQUAL (const_vector:V1SI [
> (const_int -1 [0xffffffffffffffff])
> ])
> (nil)))
>
> we can convert it to
>
> (insn 12 2 7 2 (set (reg:SI 5 di)
> (const_int -1 [0xffffffffffffffff])) "pr121062-2.c":10:3 100
> {*movsi_int
> ernal}
> (nil))
>
> Co-Developed-by: H.J. Lu <hjl.to...@gmail.com>
>
> gcc/
>
> PR target/121062
> * config/i386/i386.cc (ix86_convert_const_vector_to_integer):
> Handle E_V1SImode and E_V1DImode.
> * config/i386/mmx.md (V_16_32_64): Add V1SI, V2BF and V1DI.
> (mmxinsnmode): Add V1DI and V1SI.
> Add V_16_32_64 splitter for constant vector loads from constant
> vector pool.
> (V_16_32_64:*mov<mode>_imm): Replace lowpart_subreg with
> adjust_address.
>
> gcc/testsuite/
>
> PR target/121062
> * gcc.target/i386/pr121062-1.c: New test.
> * gcc.target/i386/pr121062-2.c: Likewise.
> * gcc.target/i386/pr121062-3a.c: Likewise.
> * gcc.target/i386/pr121062-3b.c: Likewise.
> * gcc.target/i386/pr121062-3c.c: Likewise.
> * gcc.target/i386/pr121062-4.c: Likewise.
> * gcc.target/i386/pr121062-5.c: Likewise.
> * gcc.target/i386/pr121062-6.c: Likewise.
> * gcc.target/i386/pr121062-7.c: Likewise.
>
> OK for master?
OK, with some code movements, as mentioned below.
Thanks,
Uros.
+(define_split
+ [(set (match_operand:V_16_32_64 0 "general_reg_operand")
+ (match_operand:V_16_32_64 1 "memory_operand"))]
+ "reload_completed
+ && SYMBOL_REF_P (XEXP (operands[1], 0))
+ && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
+ [(set (match_dup 0) (match_dup 1))]
...
Please put this new pattern after *movv2qi_internal as it also applies
to V2QImode and ...
@@ -417,10 +438,11 @@ (define_insn_and_split "*mov<mode>_imm"
"&& reload_completed"
[(set (match_dup 0) (match_dup 1))]
... put *mov<mode>_imm" just after the new splitter, to prevent
shadowing of *movv2qi_internal.
+ operands[0] = adjust_address (operands[0], <mmxinsnmode>mode, 0);
operands[1] = GEN_INT (val);
- operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
FYI, subregs of memory operands should be avoided, we have plenty of
helpers to change address mode or adjust address in other ways.
