Hi,
The predication of the SVE2 FP8 dot product insns was relying on the
architectural dependency:
FEAT_FP8DOT2 => FEAT_FP8DOT4
which was relaxed in GCC as of
r15-7480-g299a8e2dc667e795991bc439d2cad5ea5bd379e2, thus leading to
unrecognisable insn ICEs when compiling a two-way FDOT with just
+fp8dot2. This patch fixes the predication of the insns to test for
the correct feature bit depending on the value of the mode iterator.
Bootstrapped/regtested on aarch64-linux-gnu, OK for trunk and backport
to GCC 15?
Thanks,
Alex
gcc/ChangeLog:
PR target/120986
* config/aarch64/aarch64-sve2.md (@aarch64_sve_dot<mode>):
Adjust insn predicate to use new mode attribute which checks
for the correct feature bit depending on the mode.
(@aarch64_sve_dot_lane<mode>): Likewise.
* config/aarch64/iterators.md (HAVE_FP8_DOT_INSN): New.
gcc/testsuite/ChangeLog:
PR target/120986
* gcc.target/aarch64/torture/pr120986-1.c: New test.
---
gcc/config/aarch64/aarch64-sve2.md | 4 ++--
gcc/config/aarch64/iterators.md | 4 ++++
gcc/testsuite/gcc.target/aarch64/torture/pr120986-1.c | 10 ++++++++++
3 files changed, 16 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/torture/pr120986-1.c
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index 660901d4b3f..0c96d1305d2 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -2155,7 +2155,7 @@ (define_insn "@aarch64_sve_dot<mode>"
(match_operand:VNx16QI 3 "register_operand")
(reg:DI FPM_REGNUM)]
UNSPEC_DOT_FP8))]
- "TARGET_SSVE_FP8DOT4 && !(<MODE>mode == VNx8HFmode && !TARGET_SSVE_FP8DOT2)"
+ "<HAVE_FP8_DOT_INSN>"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
[ w , 0 , w , w ; * ] fdot\t%0.<Vetype>, %2.b, %3.b
[ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;fdot\t%0.<Vetype>, %2.b, %3.b
@@ -2171,7 +2171,7 @@ (define_insn "@aarch64_sve_dot_lane<mode>"
(match_operand:SI 4 "const_int_operand")
(reg:DI FPM_REGNUM)]
UNSPEC_DOT_LANE_FP8))]
- "TARGET_SSVE_FP8DOT4 && !(<MODE>mode == VNx8HFmode && !TARGET_SSVE_FP8DOT2)"
+ "<HAVE_FP8_DOT_INSN>"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: movprfx ]
[ w , 0 , w , y ; * ] fdot\t%0.<Vetype>, %2.b, %3.b[%4]
[ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;fdot\t%0.<Vetype>, %2.b, %3.b[%4]
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index c59fcd679d7..b5a51a8598e 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2725,6 +2725,10 @@ (define_mode_attr aligned_fpr [(VNx16QI "w") (VNx8HI "w")
(define_mode_attr LD1_EXTENDQ_MEM [(VNx4SI "VNx1SI") (VNx4SF "VNx1SI")
(VNx2DI "VNx1DI") (VNx2DF "VNx1DI")])
+(define_mode_attr HAVE_FP8_DOT_INSN [(VNx4SF "TARGET_SSVE_FP8DOT4")
+ (VNx8HF "TARGET_SSVE_FP8DOT2")])
+
+
;; -------------------------------------------------------------------
;; Code Iterators
;; -------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/aarch64/torture/pr120986-1.c b/gcc/testsuite/gcc.target/aarch64/torture/pr120986-1.c
new file mode 100644
index 00000000000..8777f1b7711
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/torture/pr120986-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.2-a+sve2+fp8dot2" } */
+#include <arm_sve.h>
+
+/* This triggered an ICE with an unrecognizable insn due to incorrect gating of
+ the insn in the backend. */
+svfloat16_t foo(svfloat16_t a, svmfloat8_t b, svmfloat8_t c, unsigned long fpm)
+{
+ return svdot_lane_fpm (a, b, c, 0, fpm);
+}
