From: Pan Li <pan2...@intel.com>
Like the avg3_floor pattern, the avg3_ceil has the
similar issue that lack of the RVV DImode support.
Thus, this patch would like to support the DImode by
the standard name, with the iterator V_VLSI_D.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/autovec.md (avg<mode>3_ceil): Add new pattern
of avg3_ceil for RVV DImode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/avg_data.h: Adjust the test data.
* gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: New test.
* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/autovec.md | 13 +++++++++++++
.../riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c | 12 ++++++++++++
.../rvv/autovec/avg_ceil-run-1-i64-from-i128.c | 16 ++++++++++++++++
.../gcc.target/riscv/rvv/autovec/avg_data.h | 2 +-
4 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 2e86826f286..da5d0e34d0a 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2532,6 +2532,19 @@ (define_expand "avg<v_double_trunc>3_ceil"
}
)
+(define_expand "avg<mode>3_ceil"
+ [(match_operand:V_VLSI_D 0 "register_operand")
+ (match_operand:V_VLSI_D 1 "register_operand")
+ (match_operand:V_VLSI_D 2 "register_operand")]
+ "TARGET_VECTOR"
+ {
+ insn_code icode = code_for_pred (UNSPEC_VAADD, <MODE>mode);
+ riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_VXRM_RNU,
+ operands);
+ DONE;
+ }
+)
+
;; csrwi vxrm, 2
;; vaaddu.vv vd, vs2, vs1
(define_expand "uavg<mode>3_floor"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
new file mode 100644
index 00000000000..64df06b27e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int64_t
+#define WT int128_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c
new file mode 100644
index 00000000000..ee5330ca8a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v && rv64 } } } */
+/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT int128_t
+#define NT int64_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a,
b, out, n)
+
+#include "avg_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
index a4a4536241d..49103f3f691 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
@@ -345,8 +345,8 @@ int64_t TEST_AVG_DATA(int64_t, avg_ceil)[][3][N] =
},
{
9223372036854775806ull, 9223372036854775806ull,
9223372036854775806ull, 9223372036854775806ull,
- 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
-2ull, -2ull,
-2ull, -2ull,
+ 9223372036854775807ull, 9223372036854775807ull,
9223372036854775807ull, 9223372036854775807ull,
-9223372036854775807ull, -9223372036854775807ull,
-9223372036854775807ull, -9223372036854775807ull,
},
{
--
2.43.0
