I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
On Wed, Jun 25, 2025 at 9:21 PM Dongyan Chen
<chendong...@isrc.iscas.ac.cn> wrote:
>
> Automatically generate -mcpu and -mtune options in invoke.texi from
> the unified riscv-cores.def metadata, ensuring documentation stays in sync
> with definitions and reducing manual maintenance.
>
> gcc/ChangeLog:
>
> * Makefile.in: Add riscv-mcpu.texi and riscv-mtune.texi to the list
> of files to be processed by the Texinfo generator.
> * config/riscv/t-riscv: Add rule for generating riscv-mcpu.texi
> and riscv-mtune.texi.
> * doc/invoke.texi: Replace hand‑written extension table with
> `@include riscv-mcpu.texi` and `@include riscv-mtune.texi` to
> pull in auto‑generated entries.
> * config/riscv/gen-riscv-mcpu-texi.cc: New file.
> * config/riscv/gen-riscv-mtune-texi.cc: New file.
> * doc/riscv-mcpu.texi: New file.
> * doc/riscv-mtune.texi: New file.
>
> ---
> gcc/Makefile.in | 2 +-
> gcc/config/riscv/gen-riscv-mcpu-texi.cc | 43 +++++++++++++++
> gcc/config/riscv/gen-riscv-mtune-texi.cc | 41 ++++++++++++++
> gcc/config/riscv/t-riscv | 37 ++++++++++++-
> gcc/doc/invoke.texi | 23 ++------
> gcc/doc/riscv-mcpu.texi | 69 ++++++++++++++++++++++++
> gcc/doc/riscv-mtune.texi | 59 ++++++++++++++++++++
> 7 files changed, 251 insertions(+), 23 deletions(-)
> create mode 100644 gcc/config/riscv/gen-riscv-mcpu-texi.cc
> create mode 100644 gcc/config/riscv/gen-riscv-mtune-texi.cc
> create mode 100644 gcc/doc/riscv-mcpu.texi
> create mode 100644 gcc/doc/riscv-mtune.texi
>
> diff --git a/gcc/Makefile.in b/gcc/Makefile.in
> index 9535804f7fb5..2d5e3427550d 100644
> --- a/gcc/Makefile.in
> +++ b/gcc/Makefile.in
> @@ -3710,7 +3710,7 @@ TEXI_GCC_FILES = gcc.texi gcc-common.texi gcc-vers.texi
> frontends.texi \
> contribute.texi compat.texi funding.texi gnu.texi gpl_v3.texi \
> fdl.texi contrib.texi cppenv.texi cppopts.texi avr-mmcu.texi \
> implement-c.texi implement-cxx.texi gcov-tool.texi gcov-dump.texi \
> - lto-dump.texi riscv-ext.texi
> + lto-dump.texi riscv-ext.texi riscv-mcpu.texi riscv-mtune.texi
>
> # we explicitly use $(srcdir)/doc/tm.texi here to avoid confusion with
> # the generated tm.texi; the latter might have a more recent timestamp,
> diff --git a/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> new file mode 100644
> index 000000000000..980a1103e0f9
> --- /dev/null
> +++ b/gcc/config/riscv/gen-riscv-mcpu-texi.cc
> @@ -0,0 +1,43 @@
> +#include <string>
> +#include <vector>
> +#include <stdio.h>
> +
> +int
> +main ()
> +{
> + puts ("@c Copyright (C) 2025 Free Software Foundation, Inc.");
> + puts ("@c This is part of the GCC manual.");
> + puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi.");
> + puts ("");
> + puts ("@c This file is generated automatically using");
> + puts ("@c gcc/config/riscv/gen-riscv-mcpu-texi.cc from:");
> + puts ("@c gcc/config/riscv/riscv-cores.def");
> + puts ("");
> + puts ("@c Please *DO NOT* edit manually.");
> + puts ("");
> + puts ("@samp{Core Name}");
> + puts ("");
> + puts ("@opindex mcpu");
> + puts ("@item -mcpu=@var{processor-string}");
> + puts ("Use architecture of and optimize the output for the given
> processor, specified");
> + puts ("by particular CPU name. Permissible values for this option are:");
> + puts ("");
> + puts ("");
> +
> + std::vector<std::string> coreNames;
> +
> +#define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) \
> + coreNames.push_back (#CORE_NAME);
> +#include "riscv-cores.def"
> +#undef RISCV_CORE
> +
> + for (size_t i = 0; i < coreNames.size(); ++i) {
> + if (i == coreNames.size() - 1) {
> + printf("@samp{%s}.\n", coreNames[i].c_str());
> + } else {
> + printf("@samp{%s},\n\n", coreNames[i].c_str());
> + }
> + }
> +
> + return 0;
> +}
> diff --git a/gcc/config/riscv/gen-riscv-mtune-texi.cc
> b/gcc/config/riscv/gen-riscv-mtune-texi.cc
> new file mode 100644
> index 000000000000..0c30b524895e
> --- /dev/null
> +++ b/gcc/config/riscv/gen-riscv-mtune-texi.cc
> @@ -0,0 +1,41 @@
> +#include <string>
> +#include <vector>
> +#include <stdio.h>
> +
> +int
> +main ()
> +{
> + puts ("@c Copyright (C) 2025 Free Software Foundation, Inc.");
> + puts ("@c This is part of the GCC manual.");
> + puts ("@c For copying conditions, see the file gcc/doc/include/fdl.texi.");
> + puts ("");
> + puts ("@c This file is generated automatically using");
> + puts ("@c gcc/config/riscv/gen-riscv-mtune-texi.cc from:");
> + puts ("@c gcc/config/riscv/riscv-cores.def");
> + puts ("");
> + puts ("@c Please *DO NOT* edit manually.");
> + puts ("");
> + puts ("@samp{Tune Name}");
> + puts ("");
> + puts ("@opindex mtune");
> + puts ("@item -mtune=@var{processor-string}");
> + puts ("Optimize the output for the given processor, specified by
> microarchitecture or");
> + puts ("particular CPU name. Permissible values for this option are:");
> + puts ("");
> + puts ("");
> +
> + std::vector<std::string> tuneNames;
> +
> +#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
> + tuneNames.push_back (#TUNE_NAME);
> +#include "riscv-cores.def"
> +#undef RISCV_TUNE
> +
> + for (size_t i = 0; i < tuneNames.size(); ++i) {
> + printf("@samp{%s},\n\n", tuneNames[i].c_str());
> + }
> +
> + puts ("and all valid options for @option{-mcpu=}.");
> +
> + return 0;
> +}
> diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
> index 32092d856878..2ddd318a2c5d 100644
> --- a/gcc/config/riscv/t-riscv
> +++ b/gcc/config/riscv/t-riscv
> @@ -228,8 +228,41 @@ s-riscv-ext.texi: build/gen-riscv-ext-texi$(build_exeext)
> $(SHELL) $(srcdir)/../move-if-change tmp-riscv-ext.texi
> $(srcdir)/doc/riscv-ext.texi
> $(STAMP) s-riscv-ext.texi
>
> -# Run `riscv-regen' after you changed or added anything from riscv-ext*.def
> +RISCV_CORES_DEFS = \
> + $(srcdir)/config/riscv/riscv-cores.def
> +
> +build/gen-riscv-mtune-texi.o: $(srcdir)/config/riscv/gen-riscv-mtune-texi.cc
> \
> + $(RISCV_CORES_DEFS)
> + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) -c $< -o $@
> +
> +build/gen-riscv-mcpu-texi.o: $(srcdir)/config/riscv/gen-riscv-mcpu-texi.cc \
> + $(RISCV_CORES_DEFS)
> + $(CXX_FOR_BUILD) $(CXXFLAGS_FOR_BUILD) -c $< -o $@
> +
> +build/gen-riscv-mtune-texi$(build_exeext): build/gen-riscv-mtune-texi.o
> + $(LINKER_FOR_BUILD) $(BUILD_LINKERFLAGS) $(BUILD_LDFLAGS) -o $@ $<
> +
> +build/gen-riscv-mcpu-texi$(build_exeext): build/gen-riscv-mcpu-texi.o
> + $(LINKER_FOR_BUILD) $(BUILD_LINKERFLAGS) $(BUILD_LDFLAGS) -o $@ $<
> +
> +$(srcdir)/doc/riscv-mtune.texi: $(RISCV_CORES_DEFS)
> +$(srcdir)/doc/riscv-mtune.texi: s-riscv-mtune.texi ; @true
> +
> +$(srcdir)/doc/riscv-mcpu.texi: $(RISCV_CORES_DEFS)
> +$(srcdir)/doc/riscv-mcpu.texi: s-riscv-mcpu.texi ; @true
> +
> +s-riscv-mtune.texi: build/gen-riscv-mtune-texi$(build_exeext)
> + $(RUN_GEN) build/gen-riscv-mtune-texi$(build_exeext) >
> tmp-riscv-mtune.texi
> + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-mtune.texi
> $(srcdir)/doc/riscv-mtune.texi
> + $(STAMP) s-riscv-mtune.texi
> +
> +s-riscv-mcpu.texi: build/gen-riscv-mcpu-texi$(build_exeext)
> + $(RUN_GEN) build/gen-riscv-mcpu-texi$(build_exeext) >
> tmp-riscv-mcpu.texi
> + $(SHELL) $(srcdir)/../move-if-change tmp-riscv-mcpu.texi
> $(srcdir)/doc/riscv-mcpu.texi
> + $(STAMP) s-riscv-mcpu.texi
> +
> +# Run `riscv-regen' after you changed or added anything from riscv-ext*.def
> and riscv-cores*.def
>
> .PHONY: riscv-regen
>
> -riscv-regen: s-riscv-ext.texi s-riscv-ext.opt
> +riscv-regen: s-riscv-ext.texi s-riscv-ext.opt s-riscv-mtune.texi
> s-riscv-mcpu.texi
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index b83818337c57..7a60eb4db38d 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -31288,31 +31288,14 @@ When the RISC-V specifications define an extension
> as depending on other
> extensions, GCC will implicitly add the dependent extensions to the enabled
> extension set if they weren't added explicitly.
>
> -@opindex mcpu
> -@item -mcpu=@var{processor-string}
> -Use architecture of and optimize the output for the given processor,
> specified
> -by particular CPU name.
> -Permissible values for this option are: @samp{mips-p8700}, @samp{sifive-e20},
> -@samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34},
> -@samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54},
> -@samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280},
> -@samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906},
> @samp{tt-ascalon-d8},
> -@samp{xiangshan-nanhu}, @samp{xiangshan-kunminghu}, @samp{xt-c908},
> @samp{xt-c908v},
> -@samp{xt-c910}, @samp{xt-c910v2}, @samp{xt-c920}, @samp{xt-c920v2}.
> +@include riscv-mcpu.texi
>
> Note that @option{-mcpu} does not override @option{-march} or
> @option{-mtune}.
>
> -@opindex mtune
> -@item -mtune=@var{processor-string}
> -Optimize the output for the given processor, specified by microarchitecture
> or
> -particular CPU name. Permissible values for this option are:
> -@samp{generic-ooo}, @samp{mips-p8700}, @samp{rocket}, @samp{sifive-3-series},
> -@samp{sifive-5-series}, @samp{sifive-7-series}, @samp{size},
> -@samp{sifive-p400-series}, @samp{sifive-p600-series}, and all valid options
> for
> -@option{-mcpu=}.
> +@include riscv-mtune.texi
>
> When @option{-mtune=} is not specified, use the setting from @option{-mcpu},
> -the default is @samp{rocket} if both are not specified.
> +the default is @samp{generic} if both are not specified.
>
> The @samp{size} choice is not intended for use by end-users. This is used
> when @option{-Os} is specified. It overrides the instruction cost info
> diff --git a/gcc/doc/riscv-mcpu.texi b/gcc/doc/riscv-mcpu.texi
> new file mode 100644
> index 000000000000..a155950f9d75
> --- /dev/null
> +++ b/gcc/doc/riscv-mcpu.texi
> @@ -0,0 +1,69 @@
> +@c Copyright (C) 2025 Free Software Foundation, Inc.
> +@c This is part of the GCC manual.
> +@c For copying conditions, see the file gcc/doc/include/fdl.texi.
> +
> +@c This file is generated automatically using
> +@c gcc/config/riscv/gen-riscv-mcpu-texi.cc from:
> +@c gcc/config/riscv/riscv-cores.def
> +
> +@c Please *DO NOT* edit manually.
> +
> +@samp{Core Name}
> +
> +@opindex mcpu
> +@item -mcpu=@var{processor-string}
> +Use architecture of and optimize the output for the given processor,
> specified
> +by particular CPU name. Permissible values for this option are:
> +
> +
> +@samp{"sifive-e20"},
> +
> +@samp{"sifive-e21"},
> +
> +@samp{"sifive-e24"},
> +
> +@samp{"sifive-e31"},
> +
> +@samp{"sifive-e34"},
> +
> +@samp{"sifive-e76"},
> +
> +@samp{"sifive-s21"},
> +
> +@samp{"sifive-s51"},
> +
> +@samp{"sifive-s54"},
> +
> +@samp{"sifive-s76"},
> +
> +@samp{"sifive-u54"},
> +
> +@samp{"sifive-u74"},
> +
> +@samp{"sifive-x280"},
> +
> +@samp{"sifive-p450"},
> +
> +@samp{"sifive-p670"},
> +
> +@samp{"thead-c906"},
> +
> +@samp{"xt-c908"},
> +
> +@samp{"xt-c908v"},
> +
> +@samp{"xt-c910"},
> +
> +@samp{"xt-c910v2"},
> +
> +@samp{"xt-c920"},
> +
> +@samp{"xt-c920v2"},
> +
> +@samp{"tt-ascalon-d8"},
> +
> +@samp{"xiangshan-nanhu"},
> +
> +@samp{"xiangshan-kunminghu"},
> +
> +@samp{"mips-p8700"}.
> diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi
> new file mode 100644
> index 000000000000..a1b9db7ffb54
> --- /dev/null
> +++ b/gcc/doc/riscv-mtune.texi
> @@ -0,0 +1,59 @@
> +@c Copyright (C) 2025 Free Software Foundation, Inc.
> +@c This is part of the GCC manual.
> +@c For copying conditions, see the file gcc/doc/include/fdl.texi.
> +
> +@c This file is generated automatically using
> +@c gcc/config/riscv/gen-riscv-mtune-texi.cc from:
> +@c gcc/config/riscv/riscv-cores.def
> +
> +@c Please *DO NOT* edit manually.
> +
> +@samp{Tune Name}
> +
> +@opindex mtune
> +@item -mtune=@var{processor-string}
> +Optimize the output for the given processor, specified by microarchitecture
> or
> +particular CPU name. Permissible values for this option are:
> +
> +
> +@samp{"generic"},
> +
> +@samp{"rocket"},
> +
> +@samp{"sifive-3-series"},
> +
> +@samp{"sifive-5-series"},
> +
> +@samp{"sifive-7-series"},
> +
> +@samp{"sifive-p400-series"},
> +
> +@samp{"sifive-p600-series"},
> +
> +@samp{"tt-ascalon-d8"},
> +
> +@samp{"thead-c906"},
> +
> +@samp{"xt-c908"},
> +
> +@samp{"xt-c908v"},
> +
> +@samp{"xt-c910"},
> +
> +@samp{"xt-c910v2"},
> +
> +@samp{"xt-c920"},
> +
> +@samp{"xt-c920v2"},
> +
> +@samp{"xiangshan-nanhu"},
> +
> +@samp{"xiangshan-kunminghu"},
> +
> +@samp{"generic-ooo"},
> +
> +@samp{"size"},
> +
> +@samp{"mips-p8700"},
> +
> +and all valid options for @option{-mcpu=}.
> --
> 2.43.0
>
