This patch continues the work of making ACLE intrinsics use VNx16BI
for svbool_t results. It deals with the svcmp*_wide intrinsics.
Since the only uses of these patterns are for ACLE intrinsics,
there didn't seem much point adding an "_acle" suffix.
gcc/
* config/aarch64/aarch64.cc (@aarch64_pred_cmp<cmp_op><mode>_wide):
Split into VNx16QI_ONLY and SVE_FULL_HSI patterns. Use VNx16BI
results for both.
(*aarch64_pred_cmp<cmp_op><mode>_wide): New pattern.
(*aarch64_pred_cmp<cmp_op><mode>_wide_cc): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/cmpeq_5.c: New test.
* gcc.target/aarch64/sve/acle/general/cmpge_7.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmpge_8.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmpgt_7.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmpgt_8.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmple_7.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmple_8.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmplt_7.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmplt_8.c: Likewise.
* gcc.target/aarch64/sve/acle/general/cmpne_4.c: Likewise.
---
gcc/config/aarch64/aarch64-sve.md | 89 ++++++++++++++++++-
.../aarch64/sve/acle/general/cmpeq_5.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmpge_7.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmpge_8.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmpgt_7.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmpgt_8.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmple_7.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmple_8.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmplt_7.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmplt_8.c | 52 +++++++++++
.../aarch64/sve/acle/general/cmpne_4.c | 52 +++++++++++
11 files changed, 608 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c
diff --git a/gcc/config/aarch64/aarch64-sve.md
b/gcc/config/aarch64/aarch64-sve.md
index 1a37ece49ac..f7131bb0d2e 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -8612,7 +8612,7 @@ (define_insn "@aarch64_pred_cmp<cmp_op><mode>_wide"
[(match_operand:<VPRED> 1 "register_operand")
(match_operand:SI 2 "aarch64_sve_ptrue_flag")
(unspec:<VPRED>
- [(match_operand:SVE_FULL_BHSI 3 "register_operand")
+ [(match_operand:VNx16QI_ONLY 3 "register_operand")
(match_operand:VNx2DI 4 "register_operand")]
SVE_COND_INT_CMP_WIDE)]
UNSPEC_PRED_Z))
@@ -8625,6 +8625,51 @@ (define_insn "@aarch64_pred_cmp<cmp_op><mode>_wide"
}
)
+(define_expand "@aarch64_pred_cmp<cmp_op><mode>_wide"
+ [(parallel
+ [(set (match_operand:VNx16BI 0 "register_operand")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_operand:<VPRED> 1 "register_operand")
+ (match_operand:SI 2 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:SVE_FULL_HSI 3 "register_operand")
+ (match_operand:VNx2DI 4 "register_operand")]
+ SVE_COND_INT_CMP_WIDE)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_dup 5)))
+ (clobber (reg:CC_NZC CC_REGNUM))])]
+ "TARGET_SVE"
+ {
+ operands[5] = aarch64_ptrue_all (GET_MODE_UNIT_SIZE (<MODE>mode));
+ }
+)
+
+(define_insn "*aarch64_pred_cmp<cmp_op><mode>_wide"
+ [(set (match_operand:VNx16BI 0 "register_operand")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_operand:<VPRED> 1 "register_operand")
+ (match_operand:SI 2 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:SVE_FULL_HSI 3 "register_operand")
+ (match_operand:VNx2DI 4 "register_operand")]
+ SVE_COND_INT_CMP_WIDE)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_operand:<VPRED> 5 "aarch64_ptrue_all_operand")))
+ (clobber (reg:CC_NZC CC_REGNUM))]
+ "TARGET_SVE"
+ {@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ]
+ [ &Upa , Upl, , w, w; yes ]
cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
+ [ ?Upl , 0 , , w, w; yes ] ^
+ [ Upa , Upl, , w, w; no ] ^
+ }
+)
+
;; Predicated integer wide comparisons in which both the flag and
;; predicate results are interesting.
(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_cc"
@@ -8665,6 +8710,48 @@ (define_insn_and_rewrite
"*aarch64_pred_cmp<cmp_op><mode>_wide_cc"
}
)
+(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_cc"
+ [(set (reg:CC_NZC CC_REGNUM)
+ (unspec:CC_NZC
+ [(match_operand:VNx16BI 1 "register_operand")
+ (match_operand 4)
+ (match_operand:SI 5 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:<VPRED> 6 "register_operand")
+ (match_operand:SI 7 "aarch64_sve_ptrue_flag")
+ (unspec:<VPRED>
+ [(match_operand:SVE_FULL_HSI 2 "register_operand")
+ (match_operand:VNx2DI 3 "register_operand")]
+ SVE_COND_INT_CMP_WIDE)]
+ UNSPEC_PRED_Z)]
+ UNSPEC_PTEST))
+ (set (match_operand:VNx16BI 0 "register_operand")
+ (and:VNx16BI
+ (subreg:VNx16BI
+ (unspec:<VPRED>
+ [(match_dup 6)
+ (match_dup 7)
+ (unspec:<VPRED>
+ [(match_dup 2)
+ (match_dup 3)]
+ SVE_COND_INT_CMP_WIDE)]
+ UNSPEC_PRED_Z)
+ 0)
+ (match_operand:<VPRED> 8 "aarch64_ptrue_all_operand")))]
+ "TARGET_SVE
+ && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
+ {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ]
+ [ &Upa , Upl, w, w, Upl; yes ]
cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
+ [ ?Upl , 0 , w, w, Upl; yes ] ^
+ [ Upa , Upl, w, w, Upl; no ] ^
+ }
+ "&& !rtx_equal_p (operands[4], operands[6])"
+ {
+ operands[6] = copy_rtx (operands[4]);
+ operands[7] = operands[5];
+ }
+)
+
;; Predicated integer wide comparisons in which only the flags result
;; is interesting.
(define_insn_and_rewrite "*aarch64_pred_cmp<cmp_op><mode>_wide_ptest"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c
new file mode 100644
index 00000000000..2958bc2a10e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpeq_5.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmpeq p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpeq_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmpeq p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpeq_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmpeq p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpeq_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c
new file mode 100644
index 00000000000..d6abab05d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_7.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmpge p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmpge p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmpge p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c
new file mode 100644
index 00000000000..70be917ac4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpge_8.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmphs p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svuint16_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmphs p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmphs p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpge_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c
new file mode 100644
index 00000000000..0656b2931fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_7.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmpgt p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmpgt p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmpgt p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c
new file mode 100644
index 00000000000..b0a9ac87fb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpgt_8.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmphi p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svuint16_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmphi p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmphi p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpgt_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c
new file mode 100644
index 00000000000..3f3ea538b0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_7.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmple p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmple p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmple p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c
new file mode 100644
index 00000000000..01281cab9fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmple_8.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmpls p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svuint16_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmpls p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmpls p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmple_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c
new file mode 100644
index 00000000000..a4de6abb67d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_7.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmplt p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmplt p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmplt p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c
new file mode 100644
index 00000000000..0a095ebd651
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmplt_8.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmplo p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svuint16_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmplo p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmplo p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svuint32_t x, svuint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmplt_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c
new file mode 100644
index 00000000000..595e02461ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/cmpne_4.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+** test1:
+** cmpne p0\.h, p0/z, z0\.h, z1\.d
+** ret
+*/
+svbool_t
+test1 (svbool_t pg, svint16_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpne_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test2:
+** cmpne p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test2 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpne_wide (pg, x, y),
+ svptrue_b16 ());
+}
+
+/*
+** test3:
+** cmpne p0\.s, p0/z, z0\.s, z1\.d
+** ret
+*/
+svbool_t
+test3 (svbool_t pg, svint32_t x, svint64_t y)
+{
+ return svand_z (svptrue_b8 (),
+ svcmpne_wide (pg, x, y),
+ svptrue_b32 ());
+}
+
+#ifdef __cplusplus
+}
+#endif
--
2.43.0
