From: Pan Li <[email protected]>
This patch would like to try to match the the unsigned
SAT_MUL form 2, aka below:
#define DEF_SAT_U_MUL_FMT_2(T) \
T __attribute__((noinline)) \
sat_u_mul_##T##_fmt_2 (T a, T b) \
{ \
T result; \
if (__builtin_mul_overflow(a, b, &result)) \
return -1; \
else \
return result; \
}
While T is uint8_t, uint16_t, uint32_t and uint64_t.
Before this series if backend implemented usmul, we have:
_6 = .MUL_OVERFLOW (a_4(D), b_5(D));
_2 = IMAGPART_EXPR <_6>;
if (_2 != 0)
goto <bb 4>; [35.00%]
else
goto <bb 3>; [65.00%]
<bb 3> [local count: 697932184]:
_1 = REALPART_EXPR <_6>;
<bb 4> [local count: 1073741824]:
# _3 = PHI <18446744073709551615(2), _1(3)>
After this series if backend implemented usmul, we have:
_3 = .SAT_MUL (a_4(D), b_5(D));
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Pan Li (3):
Match: Add form 2 for unsigned SAT_MUL
Widening-Mul: Support unsigned scalar SAT_MUL 2
RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
gcc/match.pd | 12 +++++++
.../gcc.target/riscv/sat/sat_arith.h | 15 ++++++++
.../gcc.target/riscv/sat/sat_u_mul-3-u16.c | 11 ++++++
.../gcc.target/riscv/sat/sat_u_mul-3-u32.c | 11 ++++++
.../gcc.target/riscv/sat/sat_u_mul-3-u64.c | 11 ++++++
.../gcc.target/riscv/sat/sat_u_mul-3-u8.c | 11 ++++++
.../riscv/sat/sat_u_mul-run-3-u16.c | 15 ++++++++
.../riscv/sat/sat_u_mul-run-3-u32.c | 15 ++++++++
.../riscv/sat/sat_u_mul-run-3-u64.c | 15 ++++++++
.../gcc.target/riscv/sat/sat_u_mul-run-3-u8.c | 15 ++++++++
gcc/tree-ssa-math-opts.cc | 36 ++++++++++++++++++-
11 files changed, 166 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-3-u8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-3-u8.c
--
2.43.0