After
commit 965564eafb721f8000013a3112f1bba8d8fae32b
Author: Richard Sandiford <[email protected]>
Date: Tue Jul 29 15:58:34 2025 +0100
simplify-rtx: Simplify subregs of logic ops
combine generates
(set (zero_extract:SI (reg/v:SI 101 [ a ])
(const_int 8 [0x8])
(const_int 8 [0x8]))
(not:SI (sign_extract:SI (reg:SI 107 [ b ])
(const_int 8 [0x8])
(const_int 8 [0x8]))))
instead of
(set (zero_extract:SI (reg/v:SI 101 [ a ])
(const_int 8 [0x8])
(const_int 8 [0x8]))
(subreg:SI (not:QI (subreg:QI (sign_extract:SI (reg:SI 107 [ b ])
(const_int 8 [0x8])
(const_int 8 [0x8])) 0)) 0))
Add *one_cmplqi_ext<mode>_2 to support the new pattern.
PR target/121306
* config/i386/i386.md (*one_cmplqi_ext<mode>_2): New.
Signed-off-by: H.J. Lu <[email protected]>
---
gcc/config/i386/i386.md | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a50475bdaf4..565c7d26b25 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -15378,6 +15378,38 @@ (define_insn_and_split "*one_cmplqi_ext<mode>_1"
""
[(set_attr "type" "negnot")
(set_attr "mode" "QI")])
+
+;; Alternative 1 is needed to work around LRA limitation, see PR82524.
+(define_insn_and_split "*one_cmplqi_ext<mode>_2"
+ [(set (zero_extract:SWI248
+ (match_operand 0 "int248_register_operand" "+Q,&Q")
+ (const_int 8)
+ (const_int 8))
+ (not:SWI248
+ (match_operator:SWI248 2 "extract_operator"
+ [(match_operand 1 "int248_register_operand" "0,!Q")
+ (const_int 8)
+ (const_int 8)])))]
+ ""
+ "@
+ not{b}\t%h0
+ #"
+ "reload_completed
+ && !(rtx_equal_p (operands[0], operands[1]))"
+ [(set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (zero_extract:SWI248
+ (match_dup 1) (const_int 8) (const_int 8)))
+ (set (zero_extract:SWI248
+ (match_dup 0) (const_int 8) (const_int 8))
+ (subreg:SWI248
+ (not:QI
+ (subreg:QI
+ (match_op_dup 2
+ [(match_dup 0) (const_int 8) (const_int 8)]) 0)) 0))]
+ ""
+ [(set_attr "type" "negnot")
+ (set_attr "mode" "QI")])
;; Shift instructions
--
2.50.1
