On Sat, 2025-08-30 at 15:03 +0200, Gerald Pfeifer wrote:
> Among others remove a duplicate entry, fix grammar, and avoid a
> bizzare redirect for intel.com.
>
> Pushed.
>
> Gerald
> ---
> htdocs/gcc-14/changes.html | 19 ++++++++-----------
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> index f35432a6..87db6d25 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -1208,9 +1208,9 @@ __asm (".global __flmap_lock" "\n\t"
> <li>The SLP and loop vectorizer are now enabled for RISC-V when the vector
> extension is enabled, thanks to Ju-Zhe Zhong from
> <a href='https://rivai-ic.com.cn/'>RiVAI</a>,
> - Pan Li from <a href='https://www.intel.com/'>Intel</a>, and Robin Dapp
> + Pan Li from Intel, and Robin Dapp
> from <a href='https://www.ventanamicro.com/'>Ventana Micro</a> for
> - contributing most of the implementation!</li>
> + contributing most of the implementation.</li>
> <li>The <code>-mrvv-max-lmul=</code> option has been introduced for
> performance tuning of the loop vectorizer. The default value is
> <code>-mrvv-max-lmul=m1</code>, which limits the maximum LMUL to 1.
> @@ -1236,12 +1236,12 @@ __asm (".global __flmap_lock" "\n\t"
> Lehua Ding from <a href='https://rivai-ic.com.cn/'>RiVAI</a>.</li>
> <li>Supports the <code>target</code> attribute, which allows users to
> compile
> a function with specific extensions.</li>
> - <li><code>-march=</code> option no longer requires the architecture string
> + <li>The <code>-march=</code> option no longer requires the architecture
> string
> to be in canonical order, with only a few constraints remaining: the
> architecture string must start with <code>rv[32|64]
> wwwdocs:[i|g|e]</code>, and
> must use an underscore as the separator after a multi-letter extension.
> </li>
> - <li><code>-march=help</code> option has been introduced to dump all
> + <li><code>-march=help</code> has been introduced to list all
> supported extensions.</li>
> <li>Added experimental support for the <code>-mrvv-vector-bits=zvl</code>
> option and the <code>riscv_rvv_vector_bits</code> attribute, which
> @@ -1249,15 +1249,12 @@ __asm (".global __flmap_lock" "\n\t"
> optimized for specific vector core implementations; however, the code
> generated with this option is NOT portable between the core with
> different VLEN,
> - thanks to Pan Li from <a href="https://www.intel.com/";>Intel</a>.
> + thanks to Pan Li from Intel.
> </li>
> - <li>Support for TLS descriptors has been introduced, which can be enabled
> by
> + <li>Support for TLS descriptors has been introduced. It can be enabled by
> the <code>-mtls-dialect=desc</code> option. The default behavior can be
> - configured with <code>--with-tls=[trad|desc] wwwdocs:</code>.</li>
> - <li>Support for the TLS descriptors, this can be enabled by
> - <code>-mtls-dialect=desc</code> and the default behavior can be
> configure
> - by <code>--with-tls=[trad|desc] wwwdocs:</code>, and this feature
> require glibc 2.40,
> - thanks to Tatsuyuki Ishi from
> + configured with <code>--with-tls=[trad|desc] wwwdocs:</code>.
> + This feature requires glibc 2.40. Thanks to Tatsuyuki Ishi from
Just noticed this claim but unfortunately... this is not correct. The
RISC-V TLS desc support has not made into Glibc (even 2.42) yet.
--
Xi Ruoyao <[email protected]>
