On 9/2/25 12:59 AM, Kuan-Lin Chen wrote:
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
* config/riscv/riscv.md (truncsfbf2): Add TARGET_XANDESBFHCVT support.
(extendbfsf2): Ditto.
* config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandes/xandesbfhcvt-1.c: New test.
* gcc.target/riscv/xandes/xandesbfhcvt-2.c: New test.
---
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 326e9ff9c11..a73e52345d3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1864,8 +1864,13 @@
[(set (match_operand:BF 0 "register_operand" "=f")
(float_truncate:BF
(match_operand:SF 1 "register_operand" " f")))]
- "TARGET_ZFBFMIN"
- "fcvt.bf16.s\t%0,%1"
+ "TARGET_ZFBFMIN || TARGET_XANDESBFHCVT"
+{
+ if (TARGET_ZFBFMIN)
+ return "fcvt.bf16.s\t%0,%1";
+ else /* TARGET_XANDESBFHCVT */
+ return "nds.fcvt.bf16.s\t%0,%1";
+}
We don't generally put comments at EOL, instead they would normally go
on their own line. This stuff is so simple I'll just drop the comment
entirely.
Some folks prefer to avoid conditional code like that in patterns when
its easy to do so. One approach here would be to define an output
modifier than emits a "nds." conditionally. But I don't think it's
worth burning an output modifier for that here.
I'm just going to drop the two comments and push.
jeff
