Here is an updated patch that fixes scan dumps in the testsuite:
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-add-2.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-add-2.c
index 042dd0d5ccc..00b9222e765 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
@@ -39,5 +39,5 @@ DEF_OP_VX (add, 128, double, +)
DEF_OP_VX (add, 256, double, +)
DEF_OP_VX (add, 512, double, +)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,
\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,
\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-add-3.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-add-3.c
index fffaa12323e..4a7ede9ff32 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
@@ -39,5 +39,5 @@ DEF_OP_VI_15 (add, 128, double, +)
DEF_OP_VI_15 (add, 256, double, +)
DEF_OP_VI_15 (add, 512, double, +)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,
\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,
\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-sub-3.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-
point-sub-3.c
index 54a3adf3d10..2591fb8073d 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
@@ -39,5 +39,5 @@ DEF_OP_VI_15 (sub, 128, double, -)
DEF_OP_VI_15 (sub, 256, double, -)
DEF_OP_VI_15 (sub, 512, double, -)
-/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,
\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,\s*v[0-9]+,
\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
On 04/09/2025 13:14, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a vec_duplicate into a plus RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfadd.vv v1,v1,v2
After, we get only one:
vfadd.vf v1,v1,fa0
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfadd_vf_<mode>): New pattern to
combine vec_duplicate + vfadd.vv into vfadd.vf.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfadd.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
vfadd.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfadd-run-1-f64.c: New test.
