From: Pan Li <pan2...@intel.com>
This patch would like to try to match the the unsigned
SAT_MUL form 5, aka below:
#define DEF_SAT_U_MUL_FMT_5(NT, WT) \
NT __attribute__((noinline)) \
sat_u_mul_##NT##_from_##WT##_fmt_5 (NT a, NT b) \
{ \
WT x = (WT)a * (WT)b; \
NT hi = x >> (sizeof(NT) * 8); \
NT lo = (NT)x; \
return lo | -!!hi; \
}
The NT is uint8_t, uint16_t, uint32_t and uint64_t, while the WT
is uint128_t.
Before this series if backend implemented usmul, we have:
21 ??? <bb 2> [local count: 1073741824]:
24 ??? _34 = (unsigned long) a_8(D);
25 ??? _33 = (unsigned long) b_9(D);
26 ??? x_10 = _34 w* _33;
27 ??? _3 = x_10 >> 16;
28 ??? hi_11 = (uint16_t) _3;
29 ??? _4 = hi_11 != 0;
30 ??? _14 = (signed short) _4;
31 ??? _5 = -_14;
32 ??? lo.0_6 = (signed short) x_10;
33 ??? _7 = _5 | lo.0_6;
34 ??? _12 = (uint16_t) _7;
35 ??? return _12;
After this series if backend implemented usmul, we have:
9 ??? <bb 2> [local count: 1073741824]:
10 ??? _12 = .SAT_MUL (b_9(D), a_8(D)); [tail call]
11 ??? return _12;
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Pan Li (2):
Match: Add form 5 of unsigned SAT_MUL for widen-mul
RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for widen-mul
gcc/match.pd | 25 +++++++++++++++++++
.../gcc.target/riscv/sat/sat_arith.h | 15 +++++++++++
.../riscv/sat/sat_u_mul-6-u16-from-u128.c | 11 ++++++++
.../riscv/sat/sat_u_mul-6-u32-from-u128.c | 11 ++++++++
.../riscv/sat/sat_u_mul-6-u64-from-u128.c | 11 ++++++++
.../riscv/sat/sat_u_mul-6-u8-from-u128.c | 11 ++++++++
.../riscv/sat/sat_u_mul-run-6-u16-from-u128.c | 16 ++++++++++++
.../riscv/sat/sat_u_mul-run-6-u32-from-u128.c | 16 ++++++++++++
.../riscv/sat/sat_u_mul-run-6-u64-from-u128.c | 16 ++++++++++++
.../riscv/sat/sat_u_mul-run-6-u8-from-u128.c | 16 ++++++++++++
gcc/tree-ssa-math-opts.cc | 1 +
11 files changed, 149 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u64-from-u128.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u128.c
--
2.43.0
