Hi Artemiy, > +(define_insn "*aarch64_combine_high_low_internal<mode>" > + [(set (match_operand:<VDBL> 0 "aarch64_reg_or_mem_pair_operand" "=w") > + (vec_concat:<VDBL> > + (vec_select:VDC > + (match_operand:<VDBL> 1 "register_operand" "w") > + (match_operand:<VDBL> 3 "vect_par_cnst_hi_half")) > + (match_operand:VDC 2 "register_operand" "w")))] > + "TARGET_FLOAT && !BYTES_BIG_ENDIAN"
This should use TARGET_SIMD (most patterns in aarch64-simd.md should use that - the main exceptions are loads/stores, transfers and moves). It's worth checking if there are other uses of TARGET_FLOAT that should be fixed. Cheers, Wilco
