Re: [PATCH] RISC-V: Improve rotation detection for RISC-V

[Jeff Law]

On 9/24/25 4:15 AM, Dusan Stojkovic wrote:
This patch splits the canonical sign-bit checking idiom
into a 2-insn sequence when Zbb is available. Combine often normalizes
(xor (lshr A, (W - 1)) 1) to (ge A, 0). For width W = bitsize (mode), the
identity:

(a << 1) | (a >= 0)  ==  (a << 1) | ((a >> (W - 1)) ^ 1)  ==  ROL1 (a) ^ 1

lets us split:

(ior:X (ashift:X A 1) (ge:X A 0))

into:
   →  rotatert:X A, (W-1)
   →  xor:X        A, 1


2025-09-24  Dusan Stojkovic  <​dusan.stojko...@rt-rk.com>

         PR target/121778

gcc/ChangeLog:

         * config/riscv/riscv.md: Add define_split pattern.

gcc/testsuite/ChangeLog:

         * gcc.target/riscv/pr121778-1.c: New test.
         * gcc.target/riscv/pr121778-2.c: New test.
Thanks.  I've pushed this to the trunk.

I don't really see any good patterns to focus on for the 32bit object on 
rv64 case.

Jeff