When the ELEN is 32 in rv64, it can move a V2SI vector register into a DI GPR.
But the extract result in low-part must be zero-extended.
The following gimples are from pr111391-2.c:
_25 = (char) d.1_23;
_17 = {_25, _25, _25, _25, _25, _25, _25, _25};
a_26 = VIEW_CONVERT_EXPR<long int>(_17);
The final assembly:
vsetivli zero,2,e32,m1,ta,ma
vslidedown.vi v2,v4,1
vmv.x.s s1,v4 -> s1 must be zero-extended to prevent the bit 31 of v4[0] is 1
vmv.x.s a4,v2
slli a5,a4,32
or s1,a5,s1
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Append extend.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111391-2.c: Add expected asm.
---
gcc/config/riscv/riscv.cc | 6 ++++++
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1ba6cbcb2f8..28236cb6141 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3747,6 +3747,12 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx
src)
riscv_vector::emit_vec_extract (result, v,
gen_int_mode (index + i, Pmode));
+ /* The low-part must be zero-extended when ELEN == 32 and
+ mode == 64. */
+ if (num == 2 && i == 0)
+ emit_insn (gen_extend_insn (int_reg, result, mode, smode,
+ true));
+
if (i == 1)
{
if (UNITS_PER_WORD < mode_size)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c
index 32db3a68fd3..e0d757a1c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c
@@ -6,5 +6,6 @@
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*2,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vmv\.x\.s} 2 } } */
/* { dg-final { scan-assembler-times {vslidedown.vi\s+v[0-9]+,\s*v[0-9]+,\s*1}
1 } } */
-/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */
+/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,[a-x0-9]+,32} 2 } } */
+/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,[a-x0-9]+,32} 1 } } */
/* { dg-final { scan-assembler-times {or\s+[a-x0-9]+,[a-x0-9]+,[a-x0-9]+} 1 }
} */
--
2.34.1
